公开(公告)号：US07125763B1

公开(公告)日：2006-10-24

申请号：US09885426

申请日：2001-06-19

申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Mark W. Randolph

发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Mark W. Randolph

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.

摘要翻译： 一种制造存储单元的方法，该存储单元包括具有第一区域和第二区域的衬底，所述第一区域和第二区域之间具有通道，通过在衬底的沟道上形成栅极，形成位线并硅化位线。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US06795357B1

公开(公告)日：2004-09-21

申请号：US10283590

申请日：2002-10-30

申请人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

发明人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

IPC分类号： G11C700

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/26

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.

摘要翻译： 检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加 到与沟道区形成漏极结的第二位线的漏极电压。 源极电压可以是小的正电压，并且漏极电压可能大于源极电压。 将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。 偏置电压可以是负电压。

公开(公告)号：US06788583B2

公开(公告)日：2004-09-07

申请号：US10307749

申请日：2002-12-02

申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

IPC分类号： G11C1606

CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

公开(公告)号：US06477083B1

公开(公告)日：2002-11-05

申请号：US09686685

申请日：2000-10-11

申请人： Richard M. Fastow ,  Mark W. Randolph ,  Shane C. Hollmer

发明人： Richard M. Fastow ,  Mark W. Randolph ,  Shane C. Hollmer

IPC分类号： G11C1604

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/14 ,  H01L27/115

摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.

摘要翻译： 公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。 选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。 位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。

公开(公告)号：US06897110B1

公开(公告)日：2005-05-24

申请号：US10305750

申请日：2002-11-26

申请人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

发明人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.

摘要翻译： 一种制造存储器阵列的方法，同时保护其免受电荷损坏。 可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。 字线形成在位线之上，并且可以具有栅极区域。 接下来，在位线之上形成耦合到位线之一的第一金属区域。 形成不与第一金属区电耦合的第二金属区域。 然后，第一金属区域电耦合到第二金属区域。 通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。 为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。 此外，可以在位线和字线之间形成保险丝，以保护字线。

公开(公告)号：US06862221B1

公开(公告)日：2005-03-01

申请号：US10459102

申请日：2003-06-11

申请人： Ashot Melik-Martirosian ,  Mark W. Randolph ,  Sameer S. Haddad

发明人： Ashot Melik-Martirosian ,  Mark W. Randolph ,  Sameer S. Haddad

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L29/42324 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.

摘要翻译： 非易失性存储器件包括半导体衬底和衬底内的源极和漏极。 在衬底上形成电介质叠层。 电介质堆叠包括薄的顶部电介质层。 在电介质叠层上形成栅电极。 存储器装置可操作以执行直接隧道通道擦除操作，其中电荷存储层内的一对电荷存储单元通过经由薄顶介电层的直接隧穿而被擦除。

公开(公告)号：US06822909B1

公开(公告)日：2004-11-23

申请号：US10422090

申请日：2003-04-24

申请人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

发明人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

IPC分类号： G11C1134

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/3454

摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.

摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证​​阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

公开(公告)号：US06768160B1

公开(公告)日：2004-07-27

申请号：US10352658

申请日：2003-01-28

申请人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

发明人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

IPC分类号： H01L29788

CPC分类号： H01L29/78696 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792

摘要： An array of non-volatile memory cells is provided for storing a data pattern and reproducing the data pattern. The array comprises a semiconductor substrate moderately doped with a first type of impurity to enhance conductivity. A plurality of bit lines within the substrate define a plurality of vertical channel regions spaced there between. Each bit line comprises the substrate doped with a second type of impurity to enhance conductivity. Each channel comprises a moderately doped channel region portion adjacent to a first one of the bit lines and a slightly more heavily doped channel region portion adjacent to a second one of the bit lines. A plurality of parallel spaced apart semiconductor word lines are positioned over the substrate and separated from the substrate by an insulator film, a charge storage region, and a second insulator film. An array control circuit is coupled to each bit line and each word line to provide a drain bit line programming potential the second one of the bit line diffusions to accelerating electrons from the first one of the bit line diffusions towards the second one of the bit line diffusions and to provide a word line programming potential to a selected one of the word lines to divert the accelerated electrons from the channel region beneath the selected word line across the insulator film into the charge storage region.

摘要翻译： 提供了一组非易失性存储器单元，用于存储数据模式并再现数据模式。 该阵列包括适度地掺杂有第一类杂质以增强导电性的半导体衬底。 衬底内的多个位线限定了在其之间间隔开的多个垂直沟道区域。 每个位线包括掺杂有第二类杂质的衬底以增强导电性。 每个通道包括与第一位线相邻的适度掺杂的沟道区域部分和与第二位线相邻的稍高掺杂的沟道区域部分。 多个并联的间隔开的半导体字线位于衬底之上并且通过绝缘膜，电荷存储区和第二绝缘膜与衬底分离。 阵列控制电路耦合到每个位线和每个字线，以提供漏极位线编程电位，位线扩散中的第二个位加速电子从位线扩散中的第一个朝向位线的第二个 并且为所选择的一条字线提供字线编程电位，以将加速电子从所选择的字线下方的沟道区域跨过绝缘膜转移到电荷存储区域中。

公开(公告)号：US06744675B1

公开(公告)日：2004-06-01

申请号：US10305756

申请日：2002-11-26

申请人： Wei Zheng ,  Mark W. Randolph

发明人： Wei Zheng ,  Mark W. Randolph

IPC分类号： G11C1600

CPC分类号： G11C16/3413 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404

摘要： In a non-volatile SONOS-type memory device having a charge storing layer disposed between top and bottom dielectric layers, a method of programming the memory device includes selectively storing charge in an upper portion of the charge storing layer. The method includes performing a channel hot electron injection procedure followed by a soft erase operation in which charge within a bottom portion of the first charging cell is removed. A verification procedure is performed to determine whether at least one charge storing cell is in a programmed state. The method provides a programmed cell in which the stored charge is disposed adjacent an upper portion of the cell near the top dielectric.

摘要翻译： 在具有设置在顶部和底部介电层之间的电荷存储层的非易失性SONOS型存储器件中，对存储器件进行编程的方法包括在电荷存储层的上部选择性地存储电荷。 该方法包括执行通道热电子注入程序，随后进行软擦除操作，其中去除第一充电单元的底部内的电荷。 执行验证过程以确定至少一个电荷存储单元是否处于编程状态。 该方法提供了一个编程单元，其中存储的电荷邻近靠近顶部电介质的单元的上部附近设置。