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公开(公告)号：US10945062B2
公开(公告)日：2021-03-09
申请号：US16274075
申请日：2019-02-12
Applicant: Avnera Corporation
Inventor： Amit Kumar , Eric Sorensen , Shankar Rathoud
IPC: H04R3/00 , H04R29/00 , H04R1/10 , G10K11/178
Abstract: A headphone having a speaker, a feedforward microphone, a feedback microphone, and an OED processor. The speaker is configured to transmit an audio playback signal based on a headphone audio signal. The feedforward microphone is configured to sense an ambient noise signal and transmit a feedforward microphone signal based at least in part on the ambient noise signal. The feedback microphone is configured to sense a total audio signal and transmit a feedback microphone signal based at least in part on the total audio signal, in which the total audio signal is the sum of the audio playback signal and at least a portion of the ambient noise level. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on the headphone audio signal, the feedforward microphone signal, and the feedback microphone signal.
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公开(公告)号：US10581445B2
公开(公告)日：2020-03-03
申请号：US16159498
申请日：2018-10-12
Applicant: Avnera Corporation
Inventor： Jianping Wen , Garry Link , Wai Laing Lee
Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
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公开(公告)号：US10476659B2
公开(公告)日：2019-11-12
申请号：US16049474
申请日：2018-07-30
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US10448140B2
公开(公告)日：2019-10-15
申请号：US16174067
申请日：2018-10-29
Applicant: Avnera Corporation
Inventor： Amit Kumar , Shankar Rathoud , Mike Wurtz , Eric Etheridge , Eric Sorensen
IPC: H04R1/10 , H04R3/00 , H04R29/00 , G10K11/178
Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.
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公开(公告)号：US10425053B2
公开(公告)日：2019-09-24
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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Patent Agency Ranking
公开(公告)号：US10230352B2
公开(公告)日：2019-03-12
申请号：US15786500
申请日：2017-10-17
Applicant: Avnera Corporation
Inventor： Xudong Zhao
IPC: G10L21/00 , G10L19/00 , H03M13/33 , H03M13/00 , H03M13/27 , H03H17/06 , G10L21/0316 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
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公开(公告)号：US10230343B2
公开(公告)日：2019-03-12
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US10224952B2
公开(公告)日：2019-03-05
申请号：US15490759
申请日：2017-04-18
Applicant: Avnera Corporation
Inventor： Jianping Wen , Ali Hadiashar , Eric King , David Entrikin , Wai Lang Lee
IPC: H03M3/00
Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
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29.发明授权公开(公告)号：US10158373B2
公开(公告)日：2018-12-18
申请号：US15849234
申请日：2017-12-20
Applicant: Avnera Corporation
Inventor： Wai Lee , Jianping Wen , Garry N. Link
Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.
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公开(公告)号：US10142734B2
公开(公告)日：2018-11-27
申请号：US16006760
申请日：2018-06-12
Applicant: Avnera Corporation
Inventor： Theodore Hetke , John Speth
Abstract: A method for re-forming a complete ring network of a plurality of Bluetooth® speakers, after a speaker has left an original ring of speakers, the method including detecting that the speaker has left the ring, and reestablishing the ring without the departed speaker. The detection may include a timeout detection if the speaker left without notice, or include receiving notice that the speaker intends to leave.
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