公开(公告)号：US07613876B2

公开(公告)日：2009-11-03

申请号：US11450023

申请日：2006-06-08

Applicant: Rey H. Bruce ,  Noeme Paz Mateo ,  Ricky Sevilla Nite

Inventor： Rey H. Bruce ,  Noeme Paz Mateo ,  Ricky Sevilla Nite

IPC: G06F12/00

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/2022 ,  G06F2212/217

Abstract: A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

Abstract translation: 描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。 多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

公开(公告)号：US20090077306A1

公开(公告)日：2009-03-19

申请号：US12323461

申请日：2008-11-25

Applicant: Mark Ian ARCEDERA ,  Ritchie BABAYLAN ,  Reyjan LANUZA

Inventor： Mark Ian ARCEDERA ,  Ritchie BABAYLAN ,  Reyjan LANUZA

IPC: G06F12/02 ,  G06F12/00 ,  G06F3/00

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs.

Abstract translation: 为了优化存储器操作，可以使用映射表，其包括：表示多个LBA集合的逻辑字段，包括用于分别表示第一和第二LBA集合的第一和第二逻辑字段，每个表示连续LBA集合的第一和第二LBA集合 ; 表示PBA的PBA字段，包括被设置用于表示第一访问参数集的第一PBA和用于表示第二访问参数集的第二PBA，与存储器存储器中的物理存储器位置相关联的每个PBA，以及这些逻辑字段和PBA字段 被设置为将所述第一和第二LBA组与所述第一和第二PBA相关联; 并且在接收到与第一和第二LBA集相关联的I / O事务请求时，映射表使得优化的存储器操作对分别与第一和第二PBA相关联的存储器位置执行。

公开(公告)号：US20070288692A1

公开(公告)日：2007-12-13

申请号：US11450023

申请日：2006-06-08

Applicant: Rey Bruce ,  Noeme Mateo ,  Ricky Nite

Inventor： Rey Bruce ,  Noeme Mateo ,  Ricky Nite

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/2022 ,  G06F2212/217

Abstract: A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

Abstract translation: 描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。 多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

公开(公告)号：US10459842B1

公开(公告)日：2019-10-29

申请号：US15904322

申请日：2018-02-24

Applicant: BiTMICRO Networks, Inc.

Inventor： Rey H. Bruce ,  Ricardo H. Bruce ,  Marlon B. Verdan ,  Elsbeth Lauren Tagayo-Villapaña

IPC: G06F12/0862 ,  G06F9/38 ,  G06F13/16 ,  G06F3/06 ,  G06F13/28

Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

公开(公告)号：US10402315B1

公开(公告)日：2019-09-03

申请号：US15803840

申请日：2017-11-06

Applicant: BiTMICRO Networks, Inc.

Inventor： Marvin Dela Cruz Fenol ,  Jik-Jik Oyong Abad ,  Precious Nezaiah Umali Pestano

IPC: G06F12/02 ,  G06F12/0831

Abstract: In an embodiment of the invention, a method comprises: requesting an update or modification on a control data in at least one flash block in a storage memory; requesting a cache memory; replicating, from the storage memory to the cache memory, the control data to be updated or to be modified; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update or modification on the control data; and moving the dirty cache link list to a for flush link list and writing an updated control data from the for flush link list to a free flash page in the storage memory.

公开(公告)号：US10216596B1

公开(公告)日：2019-02-26

申请号：US15396557

申请日：2016-12-31

Applicant: BiTMICRO Networks, Inc.

Inventor： Bharadwaj Pudipeddi

IPC: G06F11/00 ,  G06F11/20 ,  G06F13/42 ,  G06F13/20 ,  G06F13/16 ,  G06F12/10

Abstract: Embodiments of the invention provide a system and method to vastly improve the remote write latency (write to remote server) and to reduce the load that is placed on the remote server by issuing auto-log (automatic log) writes through an integrated networking port in the SSD (solid state drive). Embodiments of the invention also provide a system and method for a PCI-e attached SSD to recover after a failure detection by appropriating a remote namespace.

公开(公告)号：US10025736B1

公开(公告)日：2018-07-17

申请号：US14690371

申请日：2015-04-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Amor Leo Saing Ricaborda ,  Alain Vincent Villaranda Abitria ,  Rose Fay M. Orcullo

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.

公开(公告)号：US09858084B2

公开(公告)日：2018-01-02

申请号：US14217399

申请日：2014-03-17

Applicant: BITMICRO Networks, Inc.

Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

IPC: G06F1/12 ,  G06F9/44 ,  G06F1/24

CPC classification number: G06F9/4401 ,  G06F1/12 ,  G06F1/24

Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.

公开(公告)号：US09842024B1

公开(公告)日：2017-12-12

申请号：US14217334

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Raquel Bautista David ,  Joey Barreto Climaco

IPC: G06F11/10 ,  G06F11/20 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F3/061 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0658 ,  G06F3/0688 ,  G06F11/2087

Abstract: In an embodiment of the invention, a method is presented to operationally integrate one or more RAID control mechanisms into a flash electronic disk controller. The method includes incorporating one or more RAID features into a flash electronic disk by adding one or more RAID components in a flash controller, wherein the flash electronic disk includes a RAID control module to control the one or more RAID components; receiving a read or write operation command at a flash controller from a host; translating the read or write operation command into a command format understood by one or more flash controllers; translating the command format into an instruction format understood by one or more flash memory devices; and accessing one or more memory locations in the one or more flash memory devices according to the instruction format to perform a read or write operation for the host.

公开(公告)号：US20140104949A1

公开(公告)日：2014-04-17

申请号：US14038684

申请日：2013-09-26

Applicant: BiTMICRO Networks, Inc.

Inventor： Rolando H. Bruce ,  Reyjan Lanuza ,  Jose Lukban ,  Mark Arcedera ,  Ryan Chong

IPC: G11C16/16

CPC classification number: G11C16/14 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract translation: 公开了一种用于减少使用至少一个擦除限制的存储器件的电子存储设备中的擦除周期的解决方案。