公开(公告)号：US20250094262A1

公开(公告)日：2025-03-20

申请号：US18787655

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Victor Wong ,  Donald Morgan

IPC: G06F11/07

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

公开(公告)号：US20250094242A1

公开(公告)日：2025-03-20

申请号：US18959384

申请日：2024-11-25

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Tony M. Brewer

IPC: G06F9/52 ,  G06F9/50

Abstract: Devices and techniques for chained resource locking are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.

公开(公告)号：US20250094086A1

公开(公告)日：2025-03-20

申请号：US18896781

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Zhengbo Wang ,  Jia Sun ,  Ming Ma

IPC: G06F3/06 ,  G06F12/06

Abstract: Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping.

公开(公告)号：US20250094085A1

公开(公告)日：2025-03-20

申请号：US18896777

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Dionisio Minopoli

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for atomic write operations are described. A memory system may determine a set of pages for an atomic write operation in which data associated with a write command is linked together for writing to a non-volatile memory. The memory system may write, to the non-volatile memory, metadata that indicates the set of pages is associated with the atomic write operation. Based on the metadata, the memory system may determine whether each page of the set of pages has been written with data for the atomic write operation. The memory system may then communicate to a host system an indication of a completion status for the atomic write operation based on determining whether each page of the set of pages has been written with the data for the atomic write operation.

公开(公告)号：US20250094043A1

公开(公告)日：2025-03-20

申请号：US18893737

申请日：2024-09-23

Applicant: Micron Technology, Inc.

Inventor： Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

公开(公告)号：US12256553B2

公开(公告)日：2025-03-18

申请号：US18144708

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

IPC: H10B53/20 ,  H01L21/02

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

公开(公告)号：US12255143B2

公开(公告)日：2025-03-18

申请号：US17187481

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L23/532 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A microelectronic device includes a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulative structures. The staircase structure has steps including edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures includes a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US12254947B2

公开(公告)日：2025-03-18

申请号：US17893966

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hirokazu Ato

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Apparatuses and methods including folded digit lines are disclosed. An example apparatus includes a first digit line portion extending in a first direction, a second digit line portion extending in the first direction, and a third digit line portion between the first and second digit line portions and extending in the first direction. A folded portion is coupled to the first and second digit line portions, and extends in a second direction and traverses the third digit line portion.

公开(公告)号：US12254926B2

公开(公告)日：2025-03-18

申请号：US17817288

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Juane Li ,  Sead Zildzic, Jr. ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

公开(公告)号：US12254401B2

公开(公告)日：2025-03-18

申请号：US17116847

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06N3/08 ,  G06F18/21 ,  G06N3/045 ,  G06T7/00

Abstract: A first artificial neural network (ANN) model implemented on a memory device can be executed on first data from an imaging device corresponding to a first image. A second ANN model implemented on the memory device can be executed on second data from the imaging device corresponding to a second, subsequent image. Whether an accuracy value of results yielded from the execution of the second ANN model on the second data is less than a threshold accuracy value can be determined by the memory device. Responsive to determining that the accuracy value is less than the threshold accuracy value, the first ANN model can be executed on third data from the imaging device corresponding to a third image subsequent to the second image. Such selection of ANN models can reduce excess power consumption of a memory device on which the ANN models are implemented.