公开(公告)号：US20120046925A1

公开(公告)日：2012-02-23

申请号：US13288741

申请日：2011-11-03

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: G06F17/10

CPC classification number: H03F1/0288 ,  H03F1/32 ,  H03F1/3247 ,  H03F2200/321

Abstract: A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a feedback digital signal at a sample rate and updating a model of the distortions based on the feedback digital signal.

Abstract translation: 公开了处理信号的方法。 该方法包括产生数字信号，将数字信号转换为模拟信号，以及产生具有失真的放大的模拟信号。 该方法还包括将放大的模拟信号以采样率转换为反馈数字信号，并基于反馈数字信号更新失真模型。

公开(公告)号：US08122189B1

公开(公告)日：2012-02-21

申请号：US12901859

申请日：2010-10-11

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G06F13/00

CPC classification number: G11C15/04 ,  H04L45/7453

Abstract: A method may include comparing a first content addressable memory (“CAM”) entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a second key value to generate multiple second comparison results; and generating a match signal if the first key value matches the first CAM entry and the second key value matches at least one of the multiple second CAM entries.

Abstract translation: 方法可以包括将第一内容可寻址存储器（“CAM”）条目与第一密钥值进行比较以生成第一比较结果; 将多个第二CAM条目中的每一个与第二密钥值进行比较以生成多个第二比较结果; 以及如果所述第一密钥值与所述第一CAM条目匹配并且所述第二密钥值与所述多个第二CAM条目中的至少一个匹配，则生成匹配信号。

公开(公告)号：US20120017049A1

公开(公告)日：2012-01-19

申请号：US13103041

申请日：2011-05-07

Applicant: David T. HASS

Inventor： David T. HASS

IPC: G06F12/08

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/30

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08064510B1

公开(公告)日：2011-11-22

申请号：US11724881

申请日：2007-03-15

Applicant: Joseph N. Babanezhad

Inventor： Joseph N. Babanezhad

IPC: H03H7/30

CPC classification number: H04B3/23 ,  H04L25/03057 ,  H04L25/03885 ,  H04L2025/03617

Abstract: A method and an apparatus for slicing an analog signal using an analog encoder.

Abstract translation: 一种使用模拟编码器对模拟信号进行分片的方法和装置。

公开(公告)号：US08040943B1

公开(公告)日：2011-10-18

申请号：US11724817

申请日：2007-03-15

Applicant: Joseph N. Babanezhad

Inventor： Joseph N. Babanezhad

IPC: H03H7/30

CPC classification number: H04B3/238 ,  H04B3/235 ,  H04L25/03012 ,  H04L25/061 ,  H04L27/06 ,  H04L2025/0349 ,  H04L2025/03617

Abstract: A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further delaying a multilevel analog signal tapped from stage n, combining the further delayed signal from stage n with an analog error signal e(t) to provide an analog weighting function Wn, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn, summing the plurality of signals XnWn, slicing a multilevel analog signal resulting from the summing of the plurality of signals XnWn using one threshold level to generate the analog error signal e(t), and combining the delayed signal from stage n with Wn.

Abstract translation: 一种使用具有一个阈值电平的二电平限幅器对多电平模拟信号进行分片以产生模拟误差信号的方法和装置。 该方法可以通过在多个串行模拟级（n）中延迟所接收的多电平模拟信号，进一步延迟从级n抽头的多电平模拟信号，将来自级n的进一步延迟的信号与模拟误差信号e（t ）以提供模拟加权函数Wn，其中来自级n的延迟信号与Wn的组合产生多个信号XnWn，对多个信号XnWn进行求和，将由多个信号求和得到的多电平模拟信号 XnWn使用一个阈值电平来产生模拟误差信号e（t），并将来自阶段n的延迟信号与Wn组合。

公开(公告)号：US08037224B2

公开(公告)日：2011-10-11

申请号：US11831887

申请日：2007-07-31

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F13/00 ,  G06F13/14 ,  G06F15/75

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08032336B2

公开(公告)日：2011-10-04

申请号：US12154157

申请日：2008-05-19

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H03F13/00 ,  G06F3/01 ,  G06F7/06 ,  H04B5/02

CPC classification number: H03F1/3247 ,  H03H21/0012 ,  H03H2021/0083 ,  H03M1/0614 ,  H03M1/1042 ,  H03M1/12

Abstract: A method of signal processing includes receiving a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal, and performing linearization, based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component. An adaptive distortion reduction system includes an input interface configured to receive a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal; and an adaptive distortion reduction module coupled to the input interface, configured to perform linearization based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component.

Abstract translation: 一种信号处理方法包括：接收包含失真分量和未失真分量的失真信号，所述失真分量至少部分归因于外生信号，并且至少部分地基于失真信号和相关信息进行信号来执行线性化 外部信号，以获得基本上类似于未失真分量的校正信号。 自适应失真减小系统包括输入接口，其被配置为接收包含失真分量和未失真分量的失真信号，所述失真分量至少部分归因于外生信号; 以及耦合到所述输入接口的自适应失真减小模块，被配置为至少部分地基于所述失真信号和与所述外生信号相关联的信息来执行线性化，以获得基本上类似于所述未失真分量的校正信号。

公开(公告)号：US08031501B1

公开(公告)日：2011-10-04

申请号：US12909714

申请日：2010-10-21

Applicant: Bindiganavale S. Nataraj ,  Chetan Deshpande ,  Vinay Iyengar ,  Sandeep Khanna

Inventor： Bindiganavale S. Nataraj ,  Chetan Deshpande ,  Vinay Iyengar ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.

Abstract translation: 本实施例描述具有分段CAM阵列的CAM设备。 CAM阵列或单元块的每个段包括一行或多行CAM单元。 基于检测到的另一个单元块的匹配条件，在搜索操作期间，CAM阵列中的一个或多个单元块被选择性地使能。 通过在搜索操作期间仅在需要时选择性地使能单元块，能量消耗降低。 选择性地启用单元块包括选择性地将匹配线预充电到单元块，选择性地使得字线到单元块，以及选择性地使能与单元块的比较线。 根据某些实施例，CAM设备可配置为以流水线方式执行搜索操作。 因此，CAM设备能够同时执行多个搜索操作。

公开(公告)号：US08023298B1

公开(公告)日：2011-09-20

申请号：US12709404

申请日：2010-02-19

Applicant: Kee Park

Inventor： Kee Park

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/1006 ,  G11C11/56 ,  G11C15/00

Abstract: Approaches for an improved encoding scheme that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power as compared to traditional binary CAMS when performing certain types of operations, such as exact matching and longest prefix matching. Encoded data words may be, but need not be, balanced data words which have equal number of logic high and logic low values.

Abstract translation: 一种用于改进编码方案的方法，其允许CAM设备选择性地在CAM设备的行的每个小区内存储二进制值的单个位或从二进制值编码的编码数据字的两位。 通过在每个CAM单元中存储编码数据字的两个比特，当执行某些类型的操作（诸如精确匹配和最长前缀匹配）时，与传统二进制CAMS相比，可以更有效地存储数据，并且CAM系统可以消耗更少的功率。 编码数据字可以是但不是必须是具有相等数量的逻辑高和逻辑低值的平衡数据字。

公开(公告)号：US07978802B1

公开(公告)日：2011-07-12

申请号：US11974362

申请日：2007-10-12

Applicant: Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

Inventor： Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0331

Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

Abstract translation: 一种用于多通道传输系统的方法和装置，其提供低等待时间操作模式，同时提供减少的车道歪斜。 整个传输系统作为中间同步系统工作，由此传输系统的每个时钟域与全局时钟树的叶节点同步。 然后使用相位对准器将每个传输通道的位和字节时钟的相位与在全局时钟树的叶节点处生成的时钟信号进行对准。