公开(公告)号：US20060020649A1

公开(公告)日：2006-01-26

申请号：US11187365

申请日：2005-07-22

Applicant: Fa Dai

Inventor： Fa Dai

IPC: G06F1/02

CPC classification number: H03M7/3042 ,  G06F1/0328 ,  G06F1/0342 ,  H03L7/16 ,  H03M7/3026

Abstract: A direct digital synthesis (DDS) circuit utilizes high order delta-sigma interpolators to remove frequency, phase and amplitude domain quantization errors. The DDS employs an n-bit accumulator operative for receiving an input frequency word (FCW) representing the desired frequency output and converts the frequency word to phase information based upon the clock frequency of the DDS. A high-order delta-sigma interpolator is configured in frequency, phase or amplitude domain to noise-shape the quantization errors through a unit defined by the transfer function of 1-(1−z−1)k in either a feedforward or feedback manner. The delta-sigma interpolator of any order can be implemented using a single-stage pipelined topology with noise transfer function of (1−z−1)k. The DDS circuit also includes digital-to-analog converters (DACs) that convert the outputted sine and cosine amplitude words to analog sinusoidal quardrature signals; and deglitch analog low-pass filters that remove the small glitches due to data conversion.

Abstract translation: 直接数字合成（DDS）电路利用高阶Δ-sigma内插器去除频率，相位和幅度域量化误差。 DDS使用n位累加器，用于接收表示所需频率输出的输入频率字（FCW），并根据DDS的时钟频率将频率字转换为相位信息。 高阶delta-sigma内插器被配置在频率，相位或幅度域中，以通过由1-（1-z）的传递函数定义的单位噪声地形成量化误差， SUP> k 以前馈或反馈方式。 任何次序的Δ-sigma内插器都可以使用具有（1-z≤-SUP）的噪声传递函数的单级流水线拓扑来实现。 DDS电路还包括将输出的正弦和余弦振幅字转换为模拟正弦曲线信号的数模转换器（DAC）; 以及去掉由于数据转换引起的小毛刺的模拟低通滤波器。

公开(公告)号：US06591230B1

公开(公告)日：2003-07-08

申请号：US09687546

申请日：2000-10-13

Applicant: Yinong Ding ,  Ching-yu Hung

Inventor： Yinong Ding ,  Ching-yu Hung

IPC: G06F300

CPC classification number: G06F1/0328

Abstract: A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards frame boundary parameters to the coprocessor (15). Parameter registers (26) in coprocessor (15) store synthesis parameters for iteratively deriving amplitude and phase values for each sample point within a data frame. Adders (28, 30, 32) generate current amplitude from one addition, and current phase value from two additions, with the results stored back into parameter registers (26). A sine function calculator circuit (34), which may use a CORDIC technique, receives the current amplitude and phase values, and generates a digital component signal for the current sample point for one of the sinusoids. Digital component signals are accumulated at the sample point in a data sample buffer (40) and output at an output (44).

Abstract translation: 用于从正弦曲线的和合成信号的协处理器（15）优选地包括具有将帧边界参数转发到协处理器（15）的主处理器（12）的电子系统（20）。 协处理器（15）中的参数寄存器（26）存储用于迭代地导出数据帧内每个采样点的幅度和相位值的合成参数。 加法器（28,30,32）从一次加法产生电流幅度，并从两次加法产生电流相位值，结果存储回参数寄存器（26）。 可以使用CORDIC技术的正弦函数计算器电路（34）接收当前的幅度和相位值，并且为一个正弦波产生用于当前采样点的数字分量信号。 数字分量信号在数据采样缓冲器（40）中的采样点累积，并在输出（44）处输出。

公开(公告)号：US06489911B1

公开(公告)日：2002-12-03

申请号：US09974489

申请日：2001-10-10

Applicant: Thomas G. O'Dwyer

Inventor： Thomas G. O'Dwyer

IPC: H03M184

CPC classification number: G06F1/0328 ,  G06J1/00 ,  H03M1/1038 ,  H03M1/1047 ,  H03M1/66

Abstract: A direct digital waveform synthesiser with DAC error correction includes a digital to analog converter system for producing a desired output waveform and having between its digital and analog output a characteristic having a linear component and a non-linear component; and a phase to amplitude converter including a storage device responsive to phase inputs to provide to the digital to analog converter system amplitudes modified to compensate for the non-linear component of a characteristic of the digital to analog converter system.

Abstract translation: 具有DAC误差校正的直接数字波形合成器包括用于产生期望的输出波形并且在其数字和模拟输出之间具有线性分量和非线性分量的特征的数模转换器系统; 以及相位到幅度转换器，其包括响应于相位输入的存储装置，以提供经修改的数模转换器系统幅度，以补偿数模转换器系统的特性的非线性分量。

公开(公告)号：US20020039396A1

公开(公告)日：2002-04-04

申请号：US09968524

申请日：2001-10-02

Applicant: NEC CORPORATION

Inventor： Filip Zalio

IPC: H04L007/00

CPC classification number: G06F1/0328

Abstract: A clock generation circuit (21) for a dual system radio frequency (RF) station, including: a digital synthesis circuit (20) clocked by a first clock signal for one RF system and adapted to generate an output having a base signal of a predetermined frequency; and filter means (31) for deriving a second clock signal for another RF system from a signal of said output, said signal having a frequency corresponding to the frequency of said second clock signal.

Abstract translation: 一种用于双系统射频（RF）站的时钟发生电路（21），包括：数字合成电路（20），其由一个RF系统的第一时钟信号计时，并且适于产生具有预定 频率; 以及用于从所述输出的信号导出另一RF系统的第二时钟信号的滤波器装置（31），所述信号具有对应于所述第二时钟信号的频率的频率。

公开(公告)号：US6075474A

公开(公告)日：2000-06-13

申请号：US105172

申请日：1998-06-26

Applicant: Pascal Gabet ,  Jean-Luc De Gouy

Inventor： Pascal Gabet ,  Jean-Luc De Gouy

IPC: H03M1/00 ,  G06F1/03 ,  H03M1/06 ,  H03M1/08 ,  H03M7/00 ,  H03M7/32 ,  H03M3/00 ,  H03M1/10

CPC classification number: G06F1/0328 ,  H03M7/3026 ,  H03M7/3037

Abstract: A device for the generation of analog signals by means of analog-digital converters comprises a block for the generation of words encoded on N bits and an analog-digital converter whose input is encoded on M bits, M being smaller than N. The device furthermore comprises a sigma-delta modulator, at the output of the first block, the bus being separated into M most significant bits reserved for the input of the analog-digital converter and N-M least significant bits that enter the sigma-delta modulator, the output of this modulator being an M-bit bus that is added to the M output bits of the word generation block by digital addition means, M being smaller than N.

Abstract translation: 用于通过模数转换器产生模拟信号的装置包括用于产生以N位编码的字的块和模拟数字转换器，其输入以M位编码，M小于N.此外，该装置 包括Σ-Δ调制器，在第一块的输出处，总线被分离为M模拟数字转换器的输入保留的最高有效位和进入Σ-Δ调制器的NM最低有效位，输出 该调制器是通过数字加法装置加到字生成块的M个输出位的M比特总线，M小于N.

公开(公告)号：US6066967A

公开(公告)日：2000-05-23

申请号：US19551

申请日：1998-02-06

Applicant: James P. Cahill ,  William M. Markowitz

Inventor： James P. Cahill ,  William M. Markowitz

IPC: G06F1/03 ,  H03L7/00 ,  G06F1/02 ,  H04L27/20

CPC classification number: H03L7/00 ,  G06F1/0328

Abstract: An improved circuit and technique for obtaining phase-coherent synthesis using a direct digital synthesizer (DDS). In the phase-coherent frequency synthesis device of the invention, a computational engine constructed from a large programmable gate array, a digital signal processing microprocessor, or a number of discrete digital logic blocks generates information sent to the DDS for generating an output frequency, .function..sub.out, which is in phase with all previous outputs of the device at the same frequency.

Abstract translation: 用于使用直接数字合成器（DDS）获得相位相干合成的改进的电路和技术。 在本发明的相位相干频率合成装置中，由大型可编程门阵列，数字信号处理微处理器或多个离散数字逻辑块构成的计算引擎产生发送到DDS的信息，用于产生输出频率fout ，其与设备的所有先前输出处于相同频率的同相。

公开(公告)号：US5892692A

公开(公告)日：1999-04-06

申请号：US941958

申请日：1997-10-01

Applicant: J. William Whikehart ,  Bradley Anderson Ballard

Inventor： J. William Whikehart ,  Bradley Anderson Ballard

IPC: G06F1/03 ,  G06F1/02

CPC classification number: G06F1/0328

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract translation: 数字波形振荡器使用查找表生成无畸变的数字化波形。 根据本发明，可以通过在单个表格内包括波形的多个周期来增加在其基本频率下使用直接查找表产生的频率。 以存储在查找表中的表长度L和周期数N的选择以优化要生成的频率的相应值和采样率的方式完成。

公开(公告)号：US5838956A

公开(公告)日：1998-11-17

申请号：US824364

申请日：1997-03-25

Applicant: Toshio Kawasaki ,  Shigemi Aizawa

Inventor： Toshio Kawasaki ,  Shigemi Aizawa

IPC: H03K3/02 ,  G06F1/03 ,  G06F1/08 ,  H03B28/00 ,  H03K4/02 ,  G06F1/04

CPC classification number: G06F1/0328 ,  G06F1/08 ,  G06F2101/04

Abstract: A clock generating circuit which generates a clock signal with a desired frequency. An adder adds a first predetermined value to a previous value stored in flip-flops to create a current value (first value). A subtractor computes the difference between a value obtained by adding a second predetermined value to the first value and a third predetermined value and outputs the resultant difference value as a second value. The first value increases every time a reference clock pulse is input. The resultant values are sent to a memory device via a selector and the flip-flops. When the first value gradually increases and finally exceeds a third predetermined value, the selector selects the second value instead of the first value, where the third predetermined value is set to the maximum address value of the memory device.

Abstract translation: 一种产生具有期望频率的时钟信号的时钟发生电路。 加法器将第一预定值与存储在触发器中的先前值相加以创建当前值（第一值）。 减法器计算通过将第二预定值与第一值相加而获得的值与第三预定值之间的差，并将所得到的差分值作为第二值输出。 每次输入参考时钟脉冲时，第一个值都会增加。 结果值通过选择器和触发器发送到存储器件。 当第一值逐渐增加并且最终超过第三预定值时，选择器选择第二值而不是第三个预定值被设置为存储器件的最大地址值。

公开(公告)号：US5495505A

公开(公告)日：1996-02-27

申请号：US630708

申请日：1990-12-20

Applicant: Thomas J. Kundmann

Inventor： Thomas J. Kundmann

IPC: G06F1/03 ,  H04L27/20 ,  H04L27/12

CPC classification number: G06F1/0328

Abstract: A direct digital frequency synthesizer increases the frequency resolution of the analog output signal by using fractionalization techniques. The best integer value I.sub.FR of a digital signal is determined and the next integer value I.sub.FR +1 of a digital signal is used to determine a weighted fractionalized value of the digital signal. The fractionalized value of the digital signal is used to synthesize the analog output signal having increased frequency resolution. In addition, IFR and IFR+1 are optimally distributed during the weighting process to ensure a minimum cumulative phase error.

Abstract translation: 直接数字频率合成器通过使用分数化技术来增加模拟输出信号的频率分辨率。 确定数字信号的最佳整数值IFR，并且使用数字信号的下一个整数值IFR + 1来确定数字信号的加权分数值。 数字信号的分数值用于合成具有增加的频率分辨率的模拟输出信号。 此外，IFR和IFR + 1在加权过程中是最佳分布的，以确保最小累积相位误差。

公开(公告)号：US5467294A

公开(公告)日：1995-11-14

申请号：US207705

申请日：1994-03-09

Applicant: Vince Hu ,  James Wang

Inventor： Vince Hu ,  James Wang

IPC: G01R31/28 ,  G06F1/03 ,  G06F1/02

CPC classification number: G06F1/0328 ,  G01R31/2841

Abstract: A method and apparatus suitable for generating programmable digital sine waves which involves converting the output of a direct digital synthesizer or numerically controlled digital oscillator to a higher frequency with a multiplier-less structure that takes advantage of the properties of trigonometric identifies for sine and cosine. Sine waves are generated digitally using a phase accumulator which is clocked at one fundamental frequency. The phase accumulator input provides a control word which determines the intermediate frequency of the direct digital synthesizer output. Taking advantage of the periodicity of the phase accumulator operation, the outputs of the accumulator are utilized to address a read only memory ROM lookup table which produces in-phase and quadrature samples of the sine wave at the intermediate frequency. The in-phase and quadrature samples are then complemented (i.e. negated) to produce an additional set of in-phase and quadrature samples which are 180.degree. out of phase from the original samples. Switching between these four possible outputs at a higher fundamental clock frequency results in the translation of the intermediate frequency output to a higher frequency.

Abstract translation: 一种适用于产生可编程数字正弦波的方法和装置，其涉及将直接数字合成器或数字控制数字振荡器的输出转换为更高频率的无乘法结构，其利用三角形的属性来识别正弦和余弦。 使用在一个基频计时的相位累加器数字地产生正弦波。 相位累加器输入提供决定直接数字合成器输出的中频的控制字。 利用相位累加器操作的周期性，利用累加器的输出来寻址在中频产生正弦波的同相和正交采样的只读存储器ROM查找表。 然后对同相和正交采样进行补码（即否定），以产生与原始采样相位相差180°的另外一组同相和正交采样。 在更高的基本时钟频率下在这四个可能输出之间切换导致中频输出转换到较高频率。