公开(公告)号：US20080158747A1

公开(公告)日：2008-07-03

申请号：US11837633

申请日：2007-08-13

申请人： Steven H. Voldman

发明人： Steven H. Voldman

IPC分类号： G06F17/50 ,  H02H9/00

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H03K19/0033 ,  H03K19/00338 ,  H01L2924/00

摘要： An ESD network. The ESD network including a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

摘要翻译： 一个ESD网络。 ESD网络包括与两个电压焊盘之间的第一电压钳位元件串联的冗余电压钳位元件。 ESD网络可以直接或通过虚拟电压焊盘连接到电源电压焊盘或信号电压焊盘。 电压钳位元件还可以包括单元电池阵列，其中阵列电气上等同于目前在ESD网络中使用的单个大型晶体管。 通过将ESD网络创建为单元单元阵列，实现比通过使用单个晶体管作为钳位或触发元件获得的优点更大的益处，例如增加的镇流电阻和对由宇宙射线和粒子产生的电路的总体损坏。

公开(公告)号：US20080115023A1

公开(公告)日：2008-05-15

申请号：US11553786

申请日：2006-10-27

申请人： Roy M. Carlson

发明人： Roy M. Carlson

IPC分类号： G01R31/28

CPC分类号： H03K19/0033 ,  G11C11/4125 ,  H03K5/1252 ,  H03K19/00338

摘要： A radiation hardened latch and a method of operation. To mitigate SET effects, the latch includes an internally located pulse rejection inverter. The pulse rejection inverter receives an input logic signal, delays it, and compares the delay logic signal to the input logic signal. If the input logic signal and the delayed logic signal are equivalent, the delayed logic signal is allowed to propagate through the pulse rejection inverter. Because the pulse rejection inverter is internally located, SET events that occur upstream or internal to the latch or on clock signaling are mitigated.

摘要翻译： 辐射硬化闩锁和操作方法。 为了减轻SET效应，锁存器包括一个内部定位的脉冲抑制逆变器。 脉冲抑制逆变器接收输入逻辑信号，将其延迟，并将延迟逻辑信号与输入逻辑信号进行比较。 如果输入逻辑信号和延迟逻辑信号是等效的，则允许延迟的逻辑信号通过脉冲抑制反相器传播。 因为脉冲抑制逆变器在内部，所以在锁存器或时钟信号上游或内部发生的SET事件得到缓解。

公开(公告)号：US07298010B1

公开(公告)日：2007-11-20

申请号：US11358391

申请日：2006-02-21

申请人： Kwok K. Ma

发明人： Kwok K. Ma

IPC分类号： H01L23/62

CPC分类号： H01L23/556 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K19/00338 ,  H01L2924/00

摘要： A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

摘要翻译： 公开了用于辐射硬化形成在SOI或体半导体衬底上的CMOS IC的复合晶体管。 复合晶体管具有与公共栅极连接串联的电路晶体管和阻塞晶体管。 阻塞晶体管的主体端子仅连接到其源极端子，而不连接到其它连接点。 阻塞晶体管用于防止在电路晶体管中发生的单事件瞬态（SET）耦合到复合晶体管外部。 类似地，当在阻塞晶体管中发生SET时，电路晶体管防止SET耦合到复合晶体管的外部。 可以使用CMOS IC中的每个晶体管的N型和P型复合晶体管来辐射硬化IC，并且可以用于形成作为CMOS IC的构建块的反相器和传输门。

公开(公告)号：US20070205799A1

公开(公告)日：2007-09-06

申请号：US11367951

申请日：2006-03-03

申请人： Matthew Von Thun

发明人： Matthew Von Thun

IPC分类号： H03K19/007

CPC分类号： H03K19/00338

摘要： A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.

摘要翻译： 辐射硬化的逻辑电路使用两个相同的逻辑路径防止SET引发的瞬态脉冲传播通过电路。 两个逻辑路径的输出被馈送到异或门，其控制门控电路。 门控电路可以是受控的通路电路和数据锁存器，可调阈值比较器或两个可控制的锁存器。 瞬态脉冲抑制是用比TMR电路中更少的电路和费用来实现的。

公开(公告)号：US20060164143A1

公开(公告)日：2006-07-27

申请号：US11041766

申请日：2005-01-24

申请人： Eric Hendrickson

发明人： Eric Hendrickson

IPC分类号： H03K3/12

CPC分类号： H03K17/162 ,  H03K3/0375 ,  H03K5/1252 ,  H03K19/00338

摘要： A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.

摘要翻译： 提出了一种减少组合逻辑中毛刺效应的方法和系统。 如果组合逻辑引起粒子诱发的单事件瞬态（SET）信号，则连接在组合逻辑和下游逻辑之间的信号路径中的毛刺减少电路将防止SET传播到下游逻辑。 毛刺减少电路用作向下游逻辑提供经SET滤波的驱动信号的信号滤波器。 毛刺减少电路接收组合逻辑的输入和组合逻辑的输出。 该输入用于启用或禁用毛刺减少电路，使得对于某些输入值，毛刺减少电路将逻辑输出信号传递到下游逻辑，并且对于其它输入值，毛刺减少电路阻止输出信号传递到下游 逻辑。

公开(公告)号：US07075337B2

公开(公告)日：2006-07-11

申请号：US10882929

申请日：2004-06-30

申请人： Neil Edward Wood ,  Devin Bayles

发明人： Neil Edward Wood ,  Devin Bayles

IPC分类号： H03K19/094

CPC分类号： H03K3/0375 ,  H03K19/00338

摘要： A method includes precharging a first dynamic node, precharging a second dynamic node, and maintaining a first logic state of a signal on the first dynamic node responsive to a second logic state of a signal on the second dynamic node. The method further includes maintaining the second logic state of the signal on the second dynamic node responsive to the first logic state of the signal on the first dynamic node.

公开(公告)号：US20060049864A1

公开(公告)日：2006-03-09

申请号：US10936141

申请日：2004-09-07

申请人： Steven Summer

发明人： Steven Summer

IPC分类号： H03K3/01

CPC分类号： H02M7/003 ,  H03K17/08104 ,  H03K17/687 ,  H03K19/00338 ,  H03K2017/0803

摘要： A radiation tolerant high-power DC/DC converter is disclosed. The converter does not incorporate radiation-hardened parts, but instead uses p-channel FET switches that have a negative gate threshold voltage. With exposure to radiation, the gate threshold voltage decreases, becoming more negative. Thus, the gate is still controllable.

公开(公告)号：US06937053B2

公开(公告)日：2005-08-30

申请号：US10463794

申请日：2003-06-17

申请人： Roy M. Carlson ,  David O. Erstad

发明人： Roy M. Carlson ,  David O. Erstad

IPC分类号： H03K19/003 ,  H03K19/007

CPC分类号： H03K19/00338

摘要： A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.

摘要翻译： 提出了一种针对单事件颠簸（SEU）来硬化Null公约逻辑（NCL）电路的系统和方法。 将电阻元件放置在NCL电路的反馈回路中可能使NCL电路硬化。 旁路元件可以与电阻元件并联放置，以增加硬化NCL电路的锁定速度。 此外，替代输入驱动器，反馈回路中的晶体管以及可包括串联连接的两个或更多个晶体管的晶体管堆叠的反相器可以使NCL电路硬化。 此外，两个NCL门可以交叉耦合以硬化NCL电路。

公开(公告)号：US20040124876A1

公开(公告)日：2004-07-01

申请号：US10335234

申请日：2002-12-30

申请人： Actel Corporation

发明人： William C. Plants

IPC分类号： H03K019/177

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU). The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。 本系统还包括一种用于校正具有配置数据以对可编程逻辑器件进行编程的可编程逻辑器件中的错误的方法。 该方法包括配置数据的背景读取。 接下来，分析配置数据的错误。 最后，修正配置数据，如果存在错误，则重写配置数据。

公开(公告)号：US20040022005A1

公开(公告)日：2004-02-05

申请号：US10452557

申请日：2003-05-30

申请人： Honeywell International Inc.

发明人： David O. Erstad

IPC分类号： H01H047/26 ,  H01H050/12

CPC分类号： H01L27/1203 ,  H01L29/78615 ,  H03K19/00338

摘要： A radiation hardening circuit that includes two series-connected transistors that can replace any single transistor in a circuit. The hardening circuit includes a resistor that has a first node and a second node, a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The first node of the resistor may be conductively connected to the drain terminal of the first transistor and the second node of the resistor is conductively connected to the body terminal of the first transistor. The hardening circuit also includes a second transistor in series with the first transistor, driven so that both transistors are off or on at any given time. The circuit is resistant to radiation-induced events due to the body bias of the first transistor, the off state of the second transistor, and the current limiting effect of the resistor.