公开(公告)号：US20040232942A1

公开(公告)日：2004-11-25

申请号：US10821533

申请日：2004-04-08

申请人： Actel Corporation

发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

IPC分类号： H03K019/177

CPC分类号： G06F15/7842 ,  G06F15/7867

摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

公开(公告)号：US20040199689A1

公开(公告)日：2004-10-07

申请号：US10802577

申请日：2004-03-16

申请人： Actel Corporation, a California Corporation

发明人： William C. Plants

IPC分类号： G06F013/00

CPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  H03K19/17736 ,  H03K19/1776

摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with s tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

摘要翻译： SRAM总线架构包括直通互连导体。 每个直通互连导体通过包括与三态缓冲器并联连接的通过晶体管的元件连接到FPGA的通用互连体系结构的路由通道。 传输晶体管和三态缓冲器由配置SRAM位控制。 一些直通互连导体通过可编程元件连接到SRAM块的地址，数据和控制信号线，而其他通过SRAM块进一步连接到SRAM总线架构。

公开(公告)号：US20040124876A1

公开(公告)日：2004-07-01

申请号：US10335234

申请日：2002-12-30

申请人： Actel Corporation

发明人： William C. Plants

IPC分类号： H03K019/177

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU). The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。 本系统还包括一种用于校正具有配置数据以对可编程逻辑器件进行编程的可编程逻辑器件中的错误的方法。 该方法包括配置数据的背景读取。 接下来，分析配置数据的错误。 最后，修正配置数据，如果存在错误，则重写配置数据。

公开(公告)号：US20040114436A1

公开(公告)日：2004-06-17

申请号：US10319782

申请日：2002-12-12

申请人： Actel Corporation

发明人： Volker Hecht ,  Robert Ullrich Broze ,  Zhezhong Peng

IPC分类号： G11C011/34

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11803

摘要： The present invention comprises a programmable interconnect cell switching circuit structure having a control gate potential node, a first floating gate flash transistor with a drain, a source, a floating gate and a control gate connected to the control gate potential node and a second floating gate flash memory transistor having a drain connected to a first programming node, a drain connected to a second programming node, a floating gate connected to the floating gate of the first floating gate flash transistor and a control gate connected to the control gate potential node, whereby either the source or the drain of the first floating gate flash transistor need to be connected outside the cell to ground during the program operation.

摘要翻译： 本发明包括具有控制栅极电势节点的可编程互连单元切换电路结构，连接到控制栅极电位节点的第一浮置栅极闪存晶体管，漏极，源极，浮动栅极和控制栅极以及第二浮动栅极 闪存晶体管，具有连接到第一编程节点的漏极，连接到第二编程节点的漏极，连接到第一浮置栅极闪存晶体管的浮置栅极的浮动栅极和连接到控制栅极电势节点的控制栅极，由此 在编程操作期间，第一浮栅闪光晶体管的源极或漏极需要连接到单元之外。

公开(公告)号：US20030218479A1

公开(公告)日：2003-11-27

申请号：US10429002

申请日：2003-04-30

申请人： Actel Corporation, a California Corporation

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao ,  Weidong Xiong

IPC分类号： H03K019/177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

摘要翻译： 一种装置包括现场可编程门阵列（FPGA）。 所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体 接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。 第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

公开(公告)号：US20030121020A1

公开(公告)日：2003-06-26

申请号：US10288778

申请日：2002-11-05

申请人： Actel Corporation, a California Corporation

发明人： Sinan Kaptanoglu

IPC分类号： G06F017/50

CPC分类号： H03K19/17736 ,  H01L27/11803

摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16null16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16null16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16null16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3null3 switch matrix. A second side of each EB 3null3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3null3 switch matrix may be coupled to the leads on the second side of second EB3null3 switch matrix by BC criss-cross extension.

公开(公告)号：US20040237021A1

公开(公告)日：2004-11-25

申请号：US10877897

申请日：2004-06-24

申请人： Actel Corporation, a California Corporation

发明人： William C. Plants

IPC分类号： G06F007/38 ,  H03K019/177 ,  H03M013/00

CPC分类号： G01R31/318519 ,  G06F11/1004

摘要： A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of configuration SRAM and user assignable SRAM by the row and column counters, performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

摘要翻译： 用于检测存储在配置SRAM中的数据中的错误的方法和FPGA中的用户可分配SRAM包括：从外部源将串行数据流提供到FPGA中，将数据从串行数据流加载到配置SRAM中，以响应由 行列计数器，响应于由行和列计数器产生的地址信号，将串行数据流中的数据加载到用户可分配SRAM中，将种子和签名从串行数据流加载到循环冗余校验电路中，将数据从配置中循环 SRAM和用户可分配的SRAM，通过循环冗余校验电路对已经从配置SRAM循环出来的数据进行错误检查，并在出现错误时产生错误信号 由错误检查电路检测。

公开(公告)号：US20030201792A1

公开(公告)日：2003-10-30

申请号：US10411627

申请日：2003-04-11

申请人： Actel Corporation, a California Corporation

发明人： Reza Asayeh

IPC分类号： H03K019/177

CPC分类号： H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.

公开(公告)号：US20030163715A1

公开(公告)日：2003-08-28

申请号：US09953580

申请日：2001-09-13

申请人： Actel Corporation

发明人： Wayne Wong

IPC分类号： H04L009/32

CPC分类号： G06F21/75 ,  G06F21/76

摘要： A method and apparatus for encrypting a data stream used to program an FPGA device comprising determining if there is at least one gap in the data stream; determining whether encryption is enabled for the at least one gap in the data stream; and encrypting the data stream, if encryption is enabled for the at least one gap. A method and apparatus for de-encrypting an encrypted data stream used to program an FPGA device comprising determining if there is at least one gap in the data stream; determining whether encryption was enabled for the at least one gap in the data stream; and de-encrypting the data stream, if encryption was enabled for the at least one gap. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种用于加密用于对FPGA设备编程的数据流的方法和装置，包括确定数据流中是否存在至少一个间隙; 确定对所述数据流中的所述至少一个间隙是否启用加密; 以及如果为所述至少一个间隙启用加密，则对所述数据流进行加密。 一种用于对用于对FPGA设备编程的加密数据流进行解加密的方法和装置，包括确定数据流中是否存在至少一个间隙; 确定对所述数据流中的所述至少一个间隙是否启用加密; 以及如果为所述至少一个间隙启用了加密，则对所述数据流进行解密。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20030160632A1

公开(公告)日：2003-08-28

申请号：US10246094

申请日：2002-09-17

申请人： Actel Corporation

发明人： Khaled A. El-Ayat

IPC分类号： H03K019/173

CPC分类号： H03K19/17748 ,  H03K19/17744 ,  H03K19/1778

摘要： The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/0 buffers may be configured to implement a large number of different output and input bus standards.

摘要翻译： 本发明公开了一种用于FPGA的输入/输出缓冲器部分的架构。 它提供了一种方便有效的寻址方案，用于寻址用于在FPGA中配置可编程输入/输出缓冲器的熔丝矩阵。 可编程I / O缓冲器可以被配置为实现大量不同的输出和输入总线标准。