公开(公告)号：US07034490B2

公开(公告)日：2006-04-25

申请号：US10816302

申请日：2004-04-02

申请人： Carl K. Sawtell ,  Paolo Menegoli

发明人： Carl K. Sawtell ,  Paolo Menegoli

IPC分类号： G05B19/16

CPC分类号： H03M7/3028 ,  G11B5/5526 ,  G11B5/5556 ,  G11B5/59605 ,  G11B7/0901 ,  G11B20/10037 ,  G11B20/10527 ,  G11B2020/00065 ,  H03M7/3031

摘要： A Hard Disk Drive VCM positioning servo loop comprises an oversampling bitstream Digital to Analog converter. The oversampling DAC is a sigma-delta converter which yields higher resolution and lower noise than Nyquist-rate DACs. This allows driving the VCM with finer level of current control for higher track density. This approach can be implemented in the VCM driver chip (“combo chip”) or in the microprocessor device either in hardware or in software, reducing significantly the development and manufacturing cost. Furthermore this approach can be utilized in combination with a VCM actuation method known as “voltage mode drive” wherein the output of the sigma-delta converter represents the voltage to be applied directly to the VCM actuator. Furthermore this approach can be utilized for optical data storage motor positioning servo loops or any other motor positioning servo loops where high dynamic and resolution is needed.

摘要翻译： 硬盘驱动器VCM定位伺服环路包括过采样比特流数模转换器。 过采样DAC是一种Σ-Δ转换器，其产生比奈奎斯特速率DAC更高的分辨率和更低的噪声。 这允许驱动VCM具有更高级别的电流控制以实现更高的轨道密度。 这种方法可以在VCM驱动器芯片（“组合芯片”）中或在微处理器设备中以硬件或软件实现，从而显着降低了开发和制造成本。 此外，该方法可以与称为“电压模式驱动”的VCM致动方法结合使用，其中Σ-Δ转换器的输出表示要直接施加到VCM致动器的电压。 此外，该方法可用于光学数据存储电机定位伺服环路或需要高动态和分辨率的任何其他电机定位伺服环路。

公开(公告)号：US20050001750A1

公开(公告)日：2005-01-06

申请号：US10847399

申请日：2004-05-18

申请人： Li-Sheng Lo ,  Tung-Tsai Liao

发明人： Li-Sheng Lo ,  Tung-Tsai Liao

IPC分类号： H03M7/32 ,  H03M7/36 ,  H03M3/00

CPC分类号： H03M7/3015 ,  H03M7/3026 ,  H03M7/3031

摘要： A Delta-Sigma modulator is disclosed, which has a Delta adder, a Sigma adder, a first latch, a second latch and a feedback generator, wherein the feedback generator provides a feedback signal to the Delta adder based on a pre-stage data signal provided by the first latch, so that the Delta adder provides a pre-stage addition signal. The Sigma adder performs an accumulation to provide an accumulative signal to the first latch, so that the first latch provides a pre-stage data signal to the second latch to enable the second latch to output a digital output signal.

摘要翻译： 公开了一种Δ-Σ调制器，其具有Δ加法器，Sigma加法器，第一锁存器，第二锁存器和反馈发生器，其中反馈发生器基于前级数据信号向Delta加法器提供反馈信号 由第一锁存器提供，使得Δ加法器提供前级加法信号。 Sigma加法器执行累加以向第一锁存器提供累加信号，使得第一锁存器向第二锁存器提供前级数据信号，以使第二锁存器能够输出数字输出信号。

公开(公告)号：US20040232868A1

公开(公告)日：2004-11-25

申请号：US10816302

申请日：2004-04-02

发明人： Carl K. Sawtell ,  Paolo Menegoli

IPC分类号： G11B005/596 ,  G05B019/18

CPC分类号： H03M7/3028 ,  G11B5/5526 ,  G11B5/5556 ,  G11B5/59605 ,  G11B7/0901 ,  G11B20/10037 ,  G11B20/10527 ,  G11B2020/00065 ,  H03M7/3031

摘要： A Hard Disk Drive VCM positioning servo loop comprises an oversampling bitstream Digital to Analog converter. The oversampling DAC is a sigma-delta converter which yields higher resolution and lower noise than Nyquist-rate DACs. This allows driving the VCM with finer level of current control for higher track density. This approach can be implemented in the VCM driver chip (nullcombo chipnull) or in the microprocessor device either in hardware or in software, reducing significantly the development and manufacturing cost. Furthermore this approach can be utilized in combination with a VCM actuation method known as nullvoltage mode drivenull wherein the output of the sigma-delta converter represents the voltage to be applied directly to the VCM actuator. Furthermore this approach can be utilized for optical data storage motor positioning servo loops or any other motor positioning servo loops where high dynamic and resolution is needed.

摘要翻译： 硬盘驱动器VCM定位伺服环路包括过采样比特流数模转换器。 过采样DAC是一种Σ-Δ转换器，其产生比奈奎斯特速率DAC更高的分辨率和更低的噪声。 这允许驱动VCM具有更高级别的电流控制以实现更高的轨道密度。 这种方法可以在VCM驱动器芯片（“组合芯片”）中或在微处理器设备中以硬件或软件实现，从而显着降低了开发和制造成本。 此外，该方法可以与称为“电压模式驱动”的VCM致动方法结合使用，其中Σ-Δ转换器的输出表示要直接施加到VCM致动器的电压。 此外，该方法可用于光学数据存储电机定位伺服环路或需要高动态和分辨率的任何其他电机定位伺服环路。

公开(公告)号：US06795004B2

公开(公告)日：2004-09-21

申请号：US10416443

申请日：2003-05-12

申请人： Toshihiko Masuda ,  Kazunobu Ohkuri

发明人： Toshihiko Masuda ,  Kazunobu Ohkuri

IPC分类号： H03M300

CPC分类号： H03F3/217 ,  H03F2200/331 ,  H03M3/388 ,  H03M3/506 ,  H03M7/3026 ,  H03M7/3031

摘要： A signal amplifier apparatus adapted for carrying out delta-sigma modulation of an input signal to carry out pulse width modulation (PWM) of that signal, to obtain a PWM signal, and to amplify this PWM signal so that a signal of a predetermined magnitude is obtained, wherein the signal amplifier apparatus includes a correction circuit for correcting an output of a quantizer provided in a delta-sigma modulation device. The correction circuit is installed in a feedback path with respect to the input side from the quantizer or immediately before a pulse width modulator to thereby correct distortion taking place in the amplifier. In addition, the signal amplifier apparatus invention compares PWM signals at the input and the output of the amplifier to correct the output of the quantizer that is provided in the delta-sigma modulation device, so as to cancel distortion taking place in the amplifier in accordance with respective rising time difference and falling time difference to thereby correct distortion.

摘要翻译： 一种信号放大器装置，适用于对输入信号进行Δ-Σ调制，以执行该信号的脉宽调制（PWM），获得PWM信号，并放大该PWM信号，使得预定幅度的信号为 其中所述信号放大器装置包括用于校正设置在Δ-Σ调制装置中的量化器的输出的校正电路。 校正电路相对于来自量化器的输入侧或紧接在脉冲宽度调制器之前安装在反馈路径中，从而校正在放大器中发生的失真。 此外，信号放大装置本发明比较放大器的输入和输出端的PWM信号，以校正在Δ-Σ调制装置中提供的量化器的输出，从而根据放大器中发生的失真消除 具有各自的上升时间差和下降时间差，从而校正失真。

公开(公告)号：US06791404B1

公开(公告)日：2004-09-14

申请号：US09346361

申请日：1999-07-01

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F338

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

公开(公告)号：US4901077A

公开(公告)日：1990-02-13

申请号：US182665

申请日：1988-04-18

申请人： Todd J. Christopher

发明人： Todd J. Christopher

IPC分类号： H03M3/04 ,  H03M3/02 ,  H03M7/32

CPC分类号： H03M7/3028 ,  H03M3/50 ,  H03M7/3031 ,  H03M7/304

摘要： A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

公开(公告)号：US09589591B2

公开(公告)日：2017-03-07

申请号：US14534592

申请日：2014-11-06

申请人： SONY CORPORATION

发明人： Yuuki Matsumura ,  Shiro Suzuki

IPC分类号： G11B20/10 ,  H03M7/30 ,  H03M3/00 ,  G11B20/00

CPC分类号： G11B20/10037 ,  G11B20/10027 ,  G11B2020/00065 ,  H03M3/30 ,  H03M7/3004 ,  H03M7/3013 ,  H03M7/3031 ,  H03M7/3044 ,  H03M7/3048

摘要： There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ΣΔ modulation and a second modulated signal obtained by subjecting the input signal to the ΣΔ modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.

摘要翻译： 提供了一种信号处理装置，包括信号一致检测部分，其检测样本，其中基于比特出现次数的值在预设时段内在多个样本之间彼此重合的值在第一调制 通过延迟通过ΣΔ调制获得的输入信号而获得的信号和通过再次对输入信号进行ΣΔ调制而获得的第二调制信号，在第一调制信号和第二调制信号之间切换以输出的信号切换部分，以及切换 控制部分，其通过由信号重合检测部分获得的基于出现次数彼此重合的值的样本中的信号切换部分来控制第一调制信号和第二调制信号之间的切换。

公开(公告)号：US08970412B2

公开(公告)日：2015-03-03

申请号：US13621819

申请日：2012-09-17

申请人： Invensense, Inc.

发明人： Derek K. Shaeffer ,  Xiang Fang

IPC分类号： H03M3/00 ,  H03M7/30

CPC分类号： H03M3/39 ,  H03M3/43 ,  H03M3/456 ,  H03M7/3015 ,  H03M7/3028 ,  H03M7/3031

摘要： A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

摘要翻译： 信号量化器包括求和结，环路滤波器，量化器和重构滤波器。 求和点响应于输入信号和调制信号，并且可操作地组合调制信号和输入信号以产生求和结输出。 环路滤波器响应于求和结输出，并且可操作地产生环路滤波器输出并且具有与其相关联的第一再生增益。 量化器响应于环路滤波器输出并且可操作以产生调制信号。 重建滤波器响应于调制信号，并且可操作地产生量化的输出信号，并具有与其相关联的第二再生增益，其基本上等于环路滤波器的再生增益。

公开(公告)号：US07859444B2

公开(公告)日：2010-12-28

申请号：US12512958

申请日：2009-07-30

申请人： Kazuhiro Yamamoto ,  Toshiyuki Okayasu

发明人： Kazuhiro Yamamoto ,  Toshiyuki Okayasu

IPC分类号： H03M1/66

CPC分类号： H03M3/51 ,  H03M3/502 ,  H03M7/3024 ,  H03M7/3031

摘要： Provided is a DA converter that converts an input digital signal into an analog signal, comprising an integrator that outputs an integration value of the digital signal for each cycle of a constant period; a level comparing section that makes a comparison to detect whether the integration value output by the integrator is in an excessive state of being greater than a prescribed reference value; a feedback section that subtracts a predetermined value from the integration value, based on the comparison result from the level comparing section; a timing information generating section that generates, for each cycle, timing information of a change point, at which a transition to the excessive state occurs, with units of temporal resolution shorter than the constant period, based on the integration value output by the integrator for the cycle and the integration value output by the integrator for an immediately prior cycle; a timing generating section that generates a pulse signal with units of temporal resolution shorter than the constant period based on the timing information; and a signal processing section that generates the analog signal based on the pulse signal.

摘要翻译： 提供了一种将输入数字信号转换为模拟信号的DA转换器，包括：对于恒定周期的每个周期输出数字信号的积分值的积分器; 电平比较部，进行比较以检测积分器输出的积分值是否处于大于规定基准值的过度状态; 基于来自所述电平比较部的比较结果，从所述积分值中减去预定值的反馈部; 定时信息生成部，基于积分器输出的积分值，对于每个周期，基于积分器输出的积分值，生成以过渡状态发生的变化点的定时信息，其中时间分辨率比恒定周期短 积分器输出的循环和积分值用于紧接在前的循环; 定时生成部，其基于所述定时信息，生成具有比所述恒定周期短的时间分辨单位的脉冲信号; 以及基于脉冲信号生成模拟信号的信号处理部。

公开(公告)号：US20090285328A1

公开(公告)日：2009-11-19

申请号：US12330279

申请日：2008-12-08

申请人： Uichi Sekimoto

发明人： Uichi Sekimoto

IPC分类号： H04L27/00

CPC分类号： H03M7/3026 ,  H03M7/3031

摘要： A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

摘要翻译： 数据调制电路具有添加输入信号的加法器和存储器件的输出信号; 以及输出电路部分，将加法器的输出信号鉴别和量化预定阈值。 存储器件接收并保持加法器的输出信号和预定信号，并将保持的信号作为存储器件的输出信号提供给加法器。