公开(公告)号：US20230376815A1

公开(公告)日：2023-11-23

申请号：US18212777

申请日：2023-06-22

申请人： Tencent Technology (Shenzhen) Company Limited

发明人： Pei Yuan ,  Shengyu Zhang

IPC分类号： G06N10/20 ,  G06F30/327

CPC分类号： G06N10/20 ,  G06F30/327

摘要： The present disclosure relates to a method and apparatus for generating a quantum state preparation circuit, a quantum chip, an electronic device, a storage medium, and a computer program product. The method includes: determining a target qubit set with a binary tree restriction and applying a single qubit flip gate to a first target sub-node qubit; applying a two-qubit phase offset gate between sub-node qubits; applying a two-qubit SWAP gate between the first target sub-node qubit and a second target sub-node qubit; taking the sub-node qubits as the root node qubit and iteratively performing until the sub-node qubits are leaf node qubits; and applying the two-qubit phase offset gate with a path restriction between leaf node qubits and applying a single qubit phase offset gate to the leaf node qubits to obtain a quantum state preparation circuit.

公开(公告)号：US11816417B2

公开(公告)日：2023-11-14

申请号：US17181429

申请日：2021-02-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Lin Chuang ,  Henry Lin ,  Szu-ju Huang ,  Yin-An Chen ,  Amos Hong

IPC分类号： G06F30/39 ,  G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

摘要： Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US11797736B2

公开(公告)日：2023-10-24

申请号：US17443815

申请日：2021-07-27

申请人： University of Florida Research Foundation, Incorporated

发明人： Swarup Bhunia ,  Abdulrahman Alaql

IPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/337

CPC分类号： G06F30/327 ,  G06F30/337 ,  G06F30/392 ,  G06F30/398

摘要： A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.

公开(公告)号：US20230334206A1

公开(公告)日：2023-10-19

申请号：US17659809

申请日：2022-04-19

申请人： Western Digital Technologies, Inc.

发明人： Ramanathan Muthiah ,  Ankur Agrawal ,  Muralitharan Jayaraman

IPC分类号： G06F30/327 ,  G06F30/392 ,  G06F12/02

CPC分类号： G06F30/327 ,  G06F30/392 ,  G06F12/0246

摘要： Aspects of a storage device are provided for efficient handling of logical metablock formation based on a heat distribution within the storage device. The storage device includes a plurality of memory dies each including a physical block, and a controller which forms a logical metablock from the physical blocks based on a location of each of the memory dies with respect to the controller. The controller stores a mapping of heat credit points to each of the physical blocks, where each of the heat credit points are associated with a respective heat level. The controller forms logical metablocks from the physical blocks based on the mapping. For instance, the controller forms different logical metablocks from physical blocks based on respective heat levels associated with memory dies including those blocks. As a result, efficient logical block formation may be achieved without significant complexity in firmware implementation.

公开(公告)号：US11775717B2

公开(公告)日：2023-10-03

申请号：US17254242

申请日：2019-12-30

申请人： CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.

发明人： Yuqian Cedric Wong ,  Shuiyin Yao ,  Hongchang Liang ,  Zhimin Tang

IPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F2119/06 ,  G06F2119/12

摘要： A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.

公开(公告)号：US11775713B2

公开(公告)日：2023-10-03

申请号：US17487423

申请日：2021-09-28

申请人： International Business Machines Corporation

发明人： Shiladitya Ghosh ,  Balaji Pulluru ,  Pradeep Joy ,  Arun Joseph ,  Wolfgang Roesner

IPC分类号： G06F30/327 ,  G06F30/12 ,  G06F119/06 ,  G06F119/02

CPC分类号： G06F30/327 ,  G06F30/12 ,  G06F2119/02 ,  G06F2119/06

摘要： To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.

公开(公告)号：US20230306174A1

公开(公告)日：2023-09-28

申请号：US18204230

申请日：2023-05-31

申请人： REZONENT CORPORATION

发明人： Ignatius Bezzam

IPC分类号： G06F30/35 ,  H03K19/096 ,  H03K19/00 ,  G06F30/36 ,  G06F30/327

CPC分类号： G06F30/35 ,  H03K19/0963 ,  H03K19/0019 ,  H03K19/0966 ,  G06F30/36 ,  G06F30/327 ,  G06F2119/06

摘要： Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US20230289502A1

公开(公告)日：2023-09-14

申请号：US18197869

申请日：2023-05-16

申请人： Battelle Memorial Institute

发明人： Adam G. Kimura ,  Andrew S. Elliott ,  Daniel A. Perkins

IPC分类号： G06F30/323 ,  G06F30/327

CPC分类号： G06F30/323 ,  G06F30/327 ,  G06F30/33

摘要： A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

公开(公告)号：US11755797B2

公开(公告)日：2023-09-12

申请号：US17202277

申请日：2021-03-15

申请人： ARTERIS, INC.

发明人： Benny Winefeld

IPC分类号： G06F30/327 ,  G06N20/00 ,  G06N3/08 ,  G06F30/35

CPC分类号： G06F30/327 ,  G06F30/35 ,  G06N3/08 ,  G06N20/00

摘要： A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

公开(公告)号：US11748538B1

公开(公告)日：2023-09-05

申请号：US17655989

申请日：2022-03-22

申请人： Pulsic Limited

发明人： Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/327 ,  G06F30/394 ,  G06F30/392 ,  G06F17/00 ,  G06F111/12

CPC分类号： G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/12

摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.