公开(公告)号：US06681473B1

公开(公告)日：2004-01-27

申请号：US10078066

申请日：2002-02-15

Applicant: Bin Liu ,  R. Kehl Sink ,  David Welsh ,  Yuanjian Xu

Inventor： Bin Liu ,  R. Kehl Sink ,  David Welsh ,  Yuanjian Xu

IPC: G02B600

CPC classification number: G02B6/3644 ,  G02B6/3676 ,  G02B6/3688 ,  G02B6/3692 ,  Y10T29/49885 ,  Y10T29/49982 ,  Y10T29/49993

Abstract: A method and apparatus hermetically sealing a fiber array block is described. In one embodiment, a fiber array plate is fabricated and an array of tapered holes formed therein. An adhering metal layer, such as a titanium, nickel and gold multilayer, is deposited upon the fiber array plate. A solder preform is positioned on the fiber array plate so that the array of holes in the solder preform corresponds to the array of holes in the array plate. Fibers having an adhering metal layer deposited thereon, are then inserted through the fiber array plate. The tapered holes make the fiber insertion process easier. The fiber array plate is then heated such that the solder preform melts causing the solder to fill any gaps between the fiber array plates and the fiber. When the solder cools a hermetic seal is formed while the fibers remain accurately positioned.

Abstract translation: 描述了密封光纤阵列块的方法和设备。 在一个实施例中，制造了光纤阵列板，并且形成了一组锥形孔。 附着的金属层，例如钛，镍和金多层，沉积在纤维阵列板上。 焊料预制件位于纤维阵列板上，使得焊料预制件中的孔阵列对应于阵列板中的孔阵列。 然后将其上沉积有附着金属层的纤维插入穿过纤维阵列板。 锥形孔使纤维插入过程更容易。 然后加热纤维阵列板，使​​得焊料预制件熔化，导致焊料填充纤维阵列板和纤维之间的任何间隙。 当焊料冷却时，在纤维保持精确定位的同时形成气密密封。

公开(公告)号：US06657503B2

公开(公告)日：2003-12-02

申请号：US10131963

申请日：2002-04-25

Applicant: Bin Liu

Inventor： Bin Liu

IPC: H03B2700

CPC classification number: H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/7203 ,  H03K3/0231 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0995

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources reduce the coupling of noise from the first power supply terminal to the output. The third current source reduces the coupling of noise from the second power supply terminal to the output.

公开(公告)号：US06518219B1

公开(公告)日：2003-02-11

申请号：US09687564

申请日：2000-10-13

Applicant: Qinghe Yang ,  Bin Liu ,  Hong Nie ,  Xuefen Liu ,  Dadong Li ,  Yahua Shi ,  Fucheng Zhuang

Inventor： Qinghe Yang ,  Bin Liu ,  Hong Nie ,  Xuefen Liu ,  Dadong Li ,  Yahua Shi ,  Fucheng Zhuang

IPC: B01J2300

CPC classification number: B01J23/85 ,  B01J21/04 ,  B01J35/0026 ,  B01J35/1019 ,  B01J35/1038 ,  B01J35/1042 ,  B01J35/1061 ,  B01J35/108 ,  B01J37/033 ,  C10G45/08

Abstract: A catalyst for hydrofining fraction oils, comprises an alumina carrier and at least one metal and/or thereof oxide of Group VIB and at least one metal and/or thereof oxide of Group VIII supported on said alumina carrier. The pore volume of said alumina carrier is not less than 0.35 ml/g, in which the pore volume of the pores having a diameter of 40-100 angstrom accounts for more than 80% of the total pore volume, the alumina carrier is prepared by a special process. The catalyst possesses relatively high hydrogenation activity.

Abstract translation: 用于加氢精馏部分油的催化剂包含氧化铝载体和至少一种VIB族的金属和/或氧化物和至少一种负载在所述氧化铝载体上的第VIII族金属和/或氧化物。 所述氧化铝载体的孔体积不小于0.35ml / g，其中直径为40-100埃的孔的孔体积占总孔体积的大于80％，氧化铝载体由 一个特殊的过程。 催化剂具有较高的氢化活性。

公开(公告)号：US06426407B1

公开(公告)日：2002-07-30

申请号：US08473888

申请日：1995-06-07

Applicant: Jacques R. Fresco ,  Bin Liu ,  Lynn C. Klotz

Inventor： Jacques R. Fresco ,  Bin Liu ,  Lynn C. Klotz

IPC: C07H2102

CPC classification number: C07H21/00 ,  C12Q1/6839

Abstract: The invention relates to compositions of matter capable of serving as residues for specific binding of third strands to double-stranded complementary nucleic acids of any base-pair sequence.

Abstract translation: 本发明涉及能够作为第三链与任何碱基对序列的双链互补核酸特异性结合的残基的物质组合物。

公开(公告)号：US5807782A

公开(公告)日：1998-09-15

申请号：US533566

申请日：1995-09-25

Applicant: Chao-Ming Koh ,  Wen-Jya Liang ,  Bin Liu

Inventor： Chao-Ming Koh ,  Wen-Jya Liang ,  Bin Liu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/88

Abstract: A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.

Abstract translation: 实现了在动态随机存取存储器（DRAM）单元上制造具有增加电容的鳍状电极的堆叠电容器的方法。 本发明消除了氮化硅蚀刻停止层的需要，其已知会在衬底中引起应力并导致缺陷。 具有鳍形部分的电容器底部电极通过在具有FET的部分完成的DRAM器件上沉积多层氧化硅和掺杂多晶硅的交替层来制造。 在形成之后，通过单个掩模步骤，节点接触多层中的衬底并沉积另一个掺杂多晶硅层，对多晶硅层和氧化物层进行构图以形成电极。 本发明的一个重要特征是，图案化多层被蚀刻到底部多晶硅层上的氧化硅层上，然后氧化硅层被各向同性地蚀刻（例如在HF中）以形成散热片电容器。 然后将鳍结构用作掩模以各向异性蚀刻底部多晶硅层，从而完成并电隔离底部鳍状电极。 通过形成电极间电介质并沉积顶部电极层来完成电容器。