公开(公告)号：US09450099B1

公开(公告)日：2016-09-20

申请号：US14743768

申请日：2015-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. The protection element has an upper portion and a lower portion between the upper portion and the gate stack, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的栅极堆叠以及栅堆叠上的保护元件。 保护元件在上部和栅极堆叠之间具有上部和下部，并且上部比下部更宽。 半导体器件结构还包括在保护元件的侧表面上的间隔元件和栅极堆叠的侧壁。 半导体器件结构还包括电连接到半导体衬底上的导电特征的导电接触。

公开(公告)号：US09401415B2

公开(公告)日：2016-07-26

申请号：US14181320

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract translation: 提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括在衬底上延伸的翅片结构和形成在鳍结构上的栅极电介质层。 FinFET器件结构还包括形成在栅极介电层上的栅电极。 FinFET器件结构还包括形成在栅电极的侧壁上的多个栅极间隔物。 栅极间隔件与翅片结构直接接触。

公开(公告)号：US09385214B2

公开(公告)日：2016-07-05

申请号：US13944009

申请日：2013-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Young Liao ,  Yi-Jen Chen ,  Yung Jung Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L22/12 ,  H01L22/20

Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.

Abstract translation: 本公开涉及一种形成可以选择性地调节以减小临界尺寸（CD）变化的栅极结构的方法。 在一些实施例中，通过在半导体衬底上形成具有第一长度的栅极结构来执行该方法。 测量栅极结构的第一长度并将其与目标长度进行比较。 如果第一长度与目标长度不同，该量大于阈值，则调整第一长度以收敛于目标长度。 通过选择性地调整栅极结构的长度，可以降低临界尺寸（CD）变化，从而提高产量并降低成本。

公开(公告)号：US09196708B2

公开(公告)日：2015-11-24

申请号：US14143789

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Yi-Jen Chen ,  Yung-Jung Chang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.

Abstract translation: 提供了一种用于形成半导体器件结构的方法的实施例。 该方法包括在半导体衬底上形成栅极叠层并在栅叠层的侧壁上形成密封结构。 该方法还包括在半导体衬底，密封结构和栅极叠层上形成虚设屏蔽层。 该方法还包括在虚拟屏蔽层上执行离子注入工艺以在半导体衬底中形成源区和漏区。 此外，该方法包括在形成源极和漏极区域之后去除虚设屏蔽层。

公开(公告)号：US20150024518A1

公开(公告)日：2015-01-22

申请号：US13944009

申请日：2013-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Young Liao ,  Yi-Jen Chen ,  Yung Jung Chang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L22/12 ,  H01L22/20

Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.

Abstract translation: 本公开涉及一种形成可以选择性地调节以减小临界尺寸（CD）变化的栅极结构的方法。 在一些实施例中，通过在半导体衬底上形成具有第一长度的栅极结构来执行该方法。 测量栅极结构的第一长度并将其与目标长度进行比较。 如果第一长度与目标长度不同，该量大于阈值，则调整第一长度以收敛于目标长度。 通过选择性地调整栅极结构的长度，可以降低临界尺寸（CD）变化，从而提高产量并降低成本。