公开(公告)号：US2738566A

公开(公告)日：1956-03-20

申请号：US50891955

申请日：1955-05-17

Applicant: CARTER WILLIAM CO

Inventor： SCOTT JR THOMAS P

IPC: D04B1/10

CPC classification number: D04B1/16 ,  D04B1/102 ,  D10B2403/0231 ,  Y10T428/24636

公开(公告)号：US2403986A

公开(公告)日：1946-07-16

申请号：US53466944

申请日：1944-05-08

Applicant: BELL TELEPHONE LABOR INC

Inventor： LACY LESTER Y

IPC: G10L21/06

CPC classification number: G10L21/06

公开(公告)号：US1744009A

公开(公告)日：1930-01-14

申请号：US33038229

申请日：1929-01-04

Applicant: GEN MOTORS CORP

Inventor： PARKER GUY E

IPC: B60K5/12

CPC classification number: B60K5/1208

公开(公告)号：US11996465B2

公开(公告)日：2024-05-28

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/22 ,  H01L29/0649 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11978530B2

公开(公告)日：2024-05-07

申请号：US17556039

申请日：2021-12-20

Applicant: STMicroelectronics SA

Inventor： Faress Tissafi Drissi

IPC: G11C7/24 ,  G11C11/419

CPC classification number: G11C7/24 ,  G11C11/419

Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.

公开(公告)号：US20240056063A1

公开(公告)日：2024-02-15

申请号：US18492597

申请日：2023-10-23

Applicant: STMICROELECTRONICS SA

Inventor： Lionel Vogt

IPC: H03K5/00

CPC classification number: H03K5/00006

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

公开(公告)号：US20240048863A1

公开(公告)日：2024-02-08

申请号：US18482117

申请日：2023-10-06

Applicant: STMicroelectronics SA

Inventor： Valentin Rebiere ,  Antoine Drouot

IPC: H04N25/60 ,  H04N23/84 ,  H04N25/13 ,  H04N25/705

CPC classification number: H04N25/60 ,  H04N23/843 ,  H04N25/13 ,  H04N25/705

Abstract: An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.

公开(公告)号：US11887982B2

公开(公告)日：2024-01-30

申请号：US17191250

申请日：2021-03-03

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H01L27/0629 ,  H02H9/046 ,  H01L28/20

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US11886214B2

公开(公告)日：2024-01-30

申请号：US17393658

申请日：2021-08-04

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt ,  Eoin Padraig O Hannaidh

IPC: G05F1/575 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.

公开(公告)号：US20240023468A1

公开(公告)日：2024-01-18

申请号：US18190901

申请日：2023-03-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Alain FLEURY ,  Stephane MONFRAY ,  Philippe CATHELIN ,  Bruno REIG ,  Vincent PUYAL

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8613 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8828

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.