公开(公告)号：US20130201771A1

公开(公告)日：2013-08-08

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

公开(公告)号：US20040256699A1

公开(公告)日：2004-12-23

申请号：US10815473

申请日：2004-04-01

Applicant: STMICROELECTRONICS SA

Inventor： Vincent Cosnier ,  Yves Morand ,  Olivier Kermarrec ,  Daniel Bensahel ,  Yves Campidelli

IPC: H01L021/336 ,  H01L031/117

CPC classification number: H01L21/28185 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/4925 ,  H01L29/51 ,  H01L29/517

Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1-xGex, where 0.5

Abstract translation: 用于制造具有由高k材料制成的栅极电介质的半导体器件的工艺和器件包括直接在栅极电介质上沉积第一层Si1-xGex的步骤，其中0.5

公开(公告)号：US20040233937A1

公开(公告)日：2004-11-25

申请号：US10826969

申请日：2004-03-31

Applicant: STMicroelectronics SA

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: G11C008/00

CPC classification number: G06F13/385

Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

Abstract translation: 异步数据传输装置包括数据接收终端，与本地时钟信号同步地接收由采样信号计时的数据。 寄存器连接到数据接收终端，用于接收数据。 时钟偏差测量电路连接到寄存器，用于确定在数据接收终端接收到的同步信号的K个周期期间出现的采样信号的周期数M，并将数M与由较低的 阈值和上限阈值。

公开(公告)号：US20040223578A1

公开(公告)日：2004-11-11

申请号：US10841705

申请日：2004-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Pierre Lagarde

IPC: H03D003/24

CPC classification number: H03L7/0994

Abstract: A circuit is provided for clock recovery from a specified datastream. The circuit includes a reference extraction unit for extracting from the datastream time references defining a reference time base, and a digital Phase Locked Loop coupled to the reference extraction unit. The digital Phase Locked Loop includes a first programmable counter in the guise of a digitally controlled oscillator for overseeing an output time base, a second programmable counter in the guise of a loop divider for overseeing a loop time base, and a dedicated processor capable of executing a program. The program includes a first software module in the guise of a phase comparator for comparing values of the loop time base and the reference time base and generating a loop error; and a second software module in the guise of a loop filter for producing an adaptation value of an increment value of the first programmable counter from the loop error. Also provided are a user terminal for an interactive telebroadcasting system that includes at least one such circuit for clock recovery, and a method for clock recovery from a specified datastream.

Abstract translation: 提供电路用于从指定的数据流中恢复时钟。 该电路包括一个参考提取单元，用于从数据流中提取定义参考时基的时间参考，以及耦合到参考提取单元的数字锁相环。 数字锁相环包括用于监视输出时基的数字控制振荡器的伪装的第一可编程计数器，用于监视环路时基的循环分配器的伪装的第二可编程计数器和能够执行的专用处理器 一个程序。 该程序包括一个相位比较器的伪装的第一软件模块，用于比较环路时基和参考时基的值并产生一个循环误差; 以及环路滤波器的伪装的第二软件模块，用于从循环误差产生第一可编程计数器的增量值的自适应值。 还提供了一种用于交互式电传广播系统的用户终端，其包括用于时钟恢复的至少一个这样的电路以及用于从指定数据流进行时钟恢复的方法。

公开(公告)号：US20040222703A1

公开(公告)日：2004-11-11

申请号：US10817629

申请日：2004-04-01

Applicant: STMicroelectronics SA

Inventor： Philippe Bienvenu ,  Sandra Mattei

IPC: H01H001/50

CPC classification number: H02H11/003 ,  H02H1/04 ,  Y10T307/931

Abstract: A device for protecting a circuit against a polarity reversal of a connection to a D.C. power supply, comprising a controllable switch interposed on said connection between a first terminal of a first voltage of the D.C. power supply and a first terminal of the circuit, and first means for turning-off with a delay the switch in the presence of a reverse polarity.

Abstract translation: 一种用于保护电路免受与直流电源的连接的极性反转的装置，包括插在所述连接上的可控开关，所述连接在所述直流电源的第一电压的第一端和所述电路的第一端之间， 用于在反向极性存在的情况下延迟关断开关的装置。

公开(公告)号：US20040217839A1

公开(公告)日：2004-11-04

申请号：US10774055

申请日：2004-02-06

Applicant: STMICROELECTRONICS SA

Inventor： Bart Van Haaren ,  Cecile Clement ,  Daniel Gloria

IPC: H01F005/00

CPC classification number: H01L28/10 ,  H01F21/12 ,  H01F2021/125 ,  H01L27/08 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: An integrated inductor comprises a first substantially plane conducting track made on the surface of a substrate and having a shape which defines a predetermined number N of concentric turns. A first pair of access points corresponds to the two respective ends of the said first conducting track. In addition, at least a second pair of access points different from the access points of the first pair, are placed at two respective regions of the first conducting track.

公开(公告)号：US20040210821A1

公开(公告)日：2004-10-21

申请号：US10799371

申请日：2004-03-12

Applicant: STMicroelectronics SA

Inventor： Bernard Kasser

IPC: G06K007/00

CPC classification number: H04L63/0428 ,  G06F21/10 ,  G06F2221/0797 ,  G06F2221/2153 ,  H04L63/062 ,  H04L63/0853

Abstract: The secure circulation of digital documents to be reproduced includes providing each user with a smart card containing identification information associated therewith, and identifying from a server connected to a digital data transmission network the smart card connected thereto. Information identifying a document to be played back is transmitted to the server from a terminal connected to the smart card. In response, a decryption key specific to the document to be reproduced is transmitted to the smart card for storing therein. The document to be played back is decrypted using an adapted reader connected to the smart card, and includes the stored decryption key for document playback with the reader. Information identifying the readers is inserted into the smart card, and fraudulent use of the smart card is determined according to the reader identification information stored in the smart card.

Abstract translation: 要再现的数字文档的安全流通包括向每个用户提供包含与其相关联的识别信息的智能卡，以及从连接到数字数据传输网络的服务器识别连接到其上的智能卡。 识别待播放文件的信息从连接到智能卡的终端发送到服务器。 作为响应，将要被再现的文档特定的解密密钥发送到智能卡以用于存储。 使用连接到智能卡的适配读取器对要播放的文档进行解密，并且包括用于与读取器进行文档回放的所存储的解密密钥。 将识别读取器的信息插入到智能卡中，并且根据存储在智能卡中的读取器识别信息确定智能卡的欺诈性使用。

公开(公告)号：US20040149808A1

公开(公告)日：2004-08-05

申请号：US10729827

申请日：2003-12-05

Applicant: STMicroelectronics SA

Inventor： Guillaume Bouche ,  Pascal Ancey ,  Benoit Froment

IPC: B23K031/02

CPC classification number: B81C1/00333 ,  H03H9/105 ,  H03H9/175

Abstract: A method for attaching a first element to a second element is provided. The first element has a surface portion covered with a layer of silicon, and the second element has a surface portion covered with a layer of nickel. The method includes applying pressure so that the surface portions of the first and second elements are in contact with one another. A roughness between the surface portions is less than about 1 nullm, and the first and second elements are heated within a range of about 250null C. to 400null C.

Abstract translation: 提供了将第一元件附接到第二元件的方法。 第一元件具有覆盖有硅层的表面部分，并且第二元件具有覆盖有镍层的表面部分。 该方法包括施加压力使得第一和第二元件的表面部分彼此接触。 表面部分之间的粗糙度小于约1um，第一和第二元件在约250℃至400℃的范围内被加热。

公开(公告)号：US20040115891A1

公开(公告)日：2004-06-17

申请号：US10689528

申请日：2003-10-20

Applicant: STMicroelectronics SA

Inventor： Yvon Gris

IPC: H01L021/336

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A process for selectively doping predetermined resistive elements on an electronic chip is provided. The resistive elements are arranged in a pattern, and there are three phases in the process. The first phase electrically charges selected elements of the pattern. The second phase adds doping atoms to the charged elements as a function of their state of charge. The third phase anneals the electronic chip to cause penetration of the doping agents and to activate them.

Abstract translation: 提供了用于在电子芯片上选择性地掺杂预定电阻元件的工艺。 电阻元件以图案布置，并且在该过程中存在三个阶段。 第一阶段对所选择的图案元素进行电荷充电。 第二阶段根据其充电状态将掺杂原子添加到带电元件。 第三阶段使电子芯片退火以引起掺杂剂的渗透并激活它们。

公开(公告)号：US20040073762A1

公开(公告)日：2004-04-15

申请号：US10645321

申请日：2003-08-21

Applicant: STMicroelectronics SA

Inventor： Franck Roche ,  Didier Cavalli

IPC: G06F012/00

CPC classification number: G06F13/4022

Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

Abstract translation: 微处理器通过第一总线连接到第一存储器空间，并通过第二总线连接到第二存储器空间。 微处理器包括一个处理单元，它包括一个程序总线和一个数据总线，一个接口单元一方面连接到程序总线和数据总线，另一侧连接到第一和第二总线。 接口包括根据访问程序和由处理单元发送的数据的相应请求，将程序总线和数据总线分别连接到第一总线或第二总线的切换电路。