公开(公告)号：US20040196912A1

公开(公告)日：2004-10-07

申请号：US10813991

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Christophe Del Toso ,  Chan-Virak Trang

IPC: H04M011/00 ,  H04M001/00

CPC classification number: H04L5/143 ,  H04B3/23 ,  H04L5/023 ,  H04L5/1438 ,  H04L25/03343 ,  H04L27/2602 ,  H04L27/2607 ,  H04L2025/03414 ,  H04L2025/03445 ,  H04L2025/03522

Abstract: Process for configuring an xDSL-type symmetric modem, comprising the following: detecting a predetermined criterion corresponding to an asymmetric operating mode, in particular an ADSL-type; and in response to said detection, disabling a number of carriers in order to establish an asymmetric operating mode. More specifically, the modem is VDSL-type, operating with up to 4096 carriers and being reconfigurable in ADSL mode with a number of carriers reduced to 256. In one case, said criterion is the detection of signals as defined in recommendation G.994.1 of the International Telecommunications Union of (ITU). Alternatively, mode switching could be controlled based on measurement of the size of the line.

Abstract translation: 用于配置xDSL型对称调制解调器的过程包括以下步骤：检测对应于非对称操作模式的预定标准，特别是ADSL型; 并且响应于所述检测，禁用多个载波以建立非对称操作模式。 更具体地说，调制解调器是VDSL型，最多可运行4096个载波，并且在ADSL模式下可重新配置，多个载波减少到256个。在一种情况下，所述标准是对ITU-T G.994.1建议G.994.1中定义的信号的检测 （国际电联）国际电信联盟。 或者，可以基于线的尺寸的测量来控制模式切换。

公开(公告)号：US20040187778A1

公开(公告)日：2004-09-30

申请号：US10720838

申请日：2003-11-24

Applicant: STMICROELECTRONICS S.A.

Inventor： Mickael Gros-Jean ,  Nicolas Jourdan ,  Jean Michailos

IPC: C23C016/00

CPC classification number: H01L21/02183 ,  C23C16/405 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/31604

Abstract: Carrier material (PL) is heated (MCH) to a heating temperature of between 200null C. and 400null C. and a gas mixture (MG) including tert-butyliminotris (diethylamino) tantalum (t-BuNnullTa(NEt2)3) is circulated in contact with the heated carrier material under an oxidizing atmosphere thereby forming a layer of tantalum pentoxide (Ta2O5) on the carrier material. The partial pressure of the tert-butyliminotris (diethylamino) tantalum is preferably greater than or equal to 25 mTorr.

Abstract translation: 将载体材料（PL）加热（MCH）至200℃至400℃的加热温度和包含叔丁基亚氨基三（二乙基氨基）钽（t-BuN = Ta（NEt2）3）的气体混合物 ）在氧化气氛下与加热的载体材料接触循环，从而在载体材料上形成五氧化二钽（Ta 2 O 5）层。 叔丁基亚氨基三（二乙基氨基）钽的分压优选大于或等于25mTorr。

公开(公告)号：US20040174945A1

公开(公告)日：2004-09-09

申请号：US10758680

申请日：2004-01-15

Applicant: STMicroelectronics S.A.

Inventor： Sandrine Lendre ,  Franck Roche ,  Olivier Plourde

IPC: H03K025/00

CPC classification number: G06F1/04

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract translation: 本发明涉及一种集成电路，其包括：传送第一时钟信号的第一时钟电路，传递第二时钟信号的第二时钟电路，用于使用时钟信号和计数值传送时基信号的第一计数电路;以及装置 用于将第一时钟信号和第一计数值应用于第一计数电路，以产生第一时基信号。 根据本发明，集成电路包括用于使用第二时钟信号和第二计数值产生第二时基信号的装置，以及用于校准第二计数值的装置，使得其等于或等于 所述第二时钟信号在等于所述第一时基信号的周期或整数个周期的确定时间间隔内发生。 尤其适用于微处理器中定时器的管理。

公开(公告)号：US20040174766A1

公开(公告)日：2004-09-09

申请号：US10738750

申请日：2003-12-17

Applicant: STMicroelectronics S.A.

Inventor： Philippe Dreux

IPC: G11C008/00

CPC classification number: G06F13/28

Abstract: A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count; at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and an adder of the first address with the counter results, said adder providing said second address.

Abstract translation: 一种可编程地址发生器，包括用于接收第一存储器中的数据字的第一数字地址的至少一个输入，以被转换为第二存储器中的该相同数据字的第二数字地址，或者相反地包括：至少两个 分层交错计数器，可以对其初始偏移量，其增量值和最大计数进行单独参数化; 至少一个包含每个计数器的参数的编程寄存器，这些参数取决于要执行的寻址转换功能; 以及具有计数器结果的第一地址的加法器，所述加法器提供所述第二地址。

公开(公告)号：US20040109336A1

公开(公告)日：2004-06-10

申请号：US10726451

申请日：2003-12-03

Applicant: STMicroelectronics S.A.

Inventor： Jerome Heurtier ,  Arnaud Florence ,  Franck Galtie

IPC: H02M007/217

CPC classification number: H03K17/22 ,  H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A controllable rectifying element, comprising a bipolar transistor having a current input terminal connected to a control terminal by a first switch and having a current output terminal connected to the control terminal by a second switch, the turn-off and turn-on phases of the first and second switches being complementary and depending on the state desired for the rectifying element.

Abstract translation: 一种可控整流元件，包括双极晶体管，其具有通过第一开关连接到控制端子的电流输入端子，并且具有通过第二开关连接到控制端子的电流输出端子，所述第二开关的断开和导通相位 第一和第二开关是互补的，并且取决于整流元件所需的状态。

公开(公告)号：US20040052148A1

公开(公告)日：2004-03-18

申请号：US10449921

申请日：2003-05-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Gendrier ,  Daniel Caspar

IPC: G11C008/02

CPC classification number: G11C17/16

Abstract: A non-volatile memory device is provided that can be irreversibly programmed electrically. The device includes a memory plane formed from a matrix of memory cells, with each of the memory cells including an access transistor and a capacitor. The memory cell matrix includes first groups of memory cells laid out in a first direction and second groups of memory cells laid out in a second direction. Each first group includes memory cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes memory cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together. The device also includes control means capable of applying chosen voltages to the first, second, and third metallizations so as to selectively program a single one of the memory cells by damaging its dielectric without programming the other memory cells and without damaging the transistors of the memory cells.

Abstract translation: 提供了可以不可逆地编程的非易失性存储器件。 该器件包括由存储器单元矩阵形成的存储器平面，每个存储器单元包括存取晶体管和电容器。 存储单元矩阵包括以第一方向布置的第一组存储器单元和沿第二方向布置的第二组存储单元。 每个第一组包括其晶体管栅极通过第一金属化连接在一起的存储单元，其上电容器电极通过第二金属化连接在一起，并且其晶体管源不连接在一起。 每个第二组包括其晶体管源通过第三金属化连接在一起的存储单元，其晶体管栅极未连接在一起，并且其上电容器电极未连接在一起。 该装置还包括能够将选择的电压施加到第一，第二和第三金属化的控制装置，以便通过损坏其电介质来选择性地编程单个存储器单元，而不对其它存储器单元进行编程，而不会损坏存储器的晶体管 细胞。

公开(公告)号：US20040041630A1

公开(公告)日：2004-03-04

申请号：US10649998

申请日：2003-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Lionel Grillo

IPC: H03F003/45

CPC classification number: H03H11/1213 ,  H03G1/0023 ,  H03H11/1291

Abstract: A low-pass filter with a variable gain comprising a transconductance differential amplifier stage comprising a differential input and a differential output, the latter receiving a passive circuit, such as a first-order RC filter, in order to realize low-pass filtering of the amplifier stage. The filter is chosen so that the cut-off frequency is below the frequency range to be treated. The filter further comprises a control element controlling the differential amplifier stage's bias point to allow control of the gain associated to filtering. Thus, low-pass filtering associated to a variable gain can be realized in a very simple way. The circuit is perfectly adapted for incorporation into a semiconductor product.

Abstract translation: 具有可变增益的低通滤波器包括跨导差分放大器级，其包括差分输入和差分输出，后者接收诸如一阶RC滤波器的无源电路，以便实现低通滤波 放大器级。 选择滤波器，使得截止频率低于待处理的频率范围。 滤波器还包括控制元件，控制差分放大器级的偏置点以允许控制与滤波有关的增益。 因此，可以以非常简单的方式实现与可变增益相关联的低通滤波。 该电路非常适合并入半导体产品。

公开(公告)号：US20040039983A1

公开(公告)日：2004-02-26

申请号：US10386123

申请日：2003-03-10

Applicant: STMicroelectronics S.A.

Inventor： Jean-Marc Brossier ,  Frederic Lehmann

IPC: H03M013/00

CPC classification number: H04L1/0042 ,  H04L1/0003 ,  H04L1/0071

Abstract: A modulation process for a digital transmission system having an error correcting code and determination of the number of bits to load on a transmission channel. The process judiciously associates a coder for introducing redundancy to the binary information, an interleaver for suppression the correlation to the encoded information and a labeling of the same based on a GRAY type coding in order to associate the said binary information with points of a constellation which is selected among a predetermined set of constellations. The process achieves a precise determination of the order and size of the constellation to utilize and, therefore, the computation of the bit loading as a function of the signal to noise ratio measured in reception and as a function of the bit error rate Pbit at the output of the receiver. The process is well adapted to the Multi Tone transmission system, and to the use of turbo codes.

Abstract translation: 一种用于具有纠错码和在传输信道上加载的比特数的确定的数字传输系统的调制过程。 该过程明确地将用于将冗余引入二进制信息的编码器，用于抑制与编码信息的相关性的交织器和基于灰度类型编码的标记，以便将所述二进制信息与星座的点相关联， 被选择在一组预定的星座中。 该过程实现了使用的星座的顺序和尺寸的精确确定，并且因此实现了在接收时测量的作为信噪比的函数的比特加载的计算，并且作为在接收时的比特误码率Pbit的函数 接收机的输出。 该过程很好地适应于多音调传输系统以及使用turbo码。

公开(公告)号：US20030169077A1

公开(公告)日：2003-09-11

申请号：US10360831

申请日：2003-02-07

Applicant: STMicroelectronics S.A.

Inventor： Benoit Dupont De Dinechin

IPC: H03K019/20

CPC classification number: G06F7/509 ,  G06F7/49921 ,  G06F7/5443

Abstract: A method for determining, by means of a circuit, a result sknull2 of an operation of the type 1 s k + 2 = ( s k null + null null a k ) null + null null a k + 1 where sk, ak, and aknull1 are fractional signed operands and symbol 2 + null represents a saturating addition operation, comprising: a step of calculation of three sums representative of a possible value of the result, and a step of selection of one of said three sums according to overflows having occurred in the sum calculation. At least one step of the method uses the positive part and the negative part of at least one of the operands.

公开(公告)号：US20030163659A1

公开(公告)日：2003-08-28

申请号：US10371400

申请日：2003-02-20

Applicant: STMicroelectronics S.A.

Inventor： Stephane Audrain

IPC: G06F012/00

CPC classification number: G06F9/3879 ,  G06F15/786

Abstract: An electronic device for data processing may include p synchronous processor cores each respectively clocked by one of p clock signals all having a same period T and being phase-shifted by 2 null/p relative to one other. The electronic device may further include a single access shared memory with an access time less than or equal to T/p. The memory may be clocked by an access signal with a period T/p and that is synchronous with the clock signals. The processors cores may sequentially and cyclically access the memory at consecutive intervals spaced apart in time with a period equal to T/p. The electronic device is particularly well suited for use in audio processors of digital versatile disk (DVD) decoders, for example.

Abstract translation: 用于数据处理的电子设备可以包括p个同步处理器核心，每个同步处理器核心分别由p个时钟信号中的一个时钟信号产生，所述p个时钟信号都具有相同的周期T并相对于彼此相移2ppi / p。 电子设备还可以包括访问时间小于或等于T / p的单个访问共享存储器。 存储器可以由具有周期T / p的访问信号来计时，并且与时钟信号同步。 处理器核可以以等于T / p的时间间隔地以连续的间隔顺序地和周期性地访问存储器。 例如，电子设备特别适用于数字通用盘（DVD）解码器的音频处理器。