公开(公告)号：US20220376100A1

公开(公告)日：2022-11-24

申请号：US17367640

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

公开(公告)号：US20220376037A1

公开(公告)日：2022-11-24

申请号：US17882596

申请日：2022-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： LINGGANG FANG

IPC: H01L49/02

Abstract: A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.

公开(公告)号：US20220373877A1

公开(公告)日：2022-11-24

申请号：US17359687

申请日：2021-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Cheng YANG ,  Chung-Yi CHIU

IPC: G03F1/36 ,  G06N20/00 ,  G06N5/04 ,  G03F7/20

Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

公开(公告)号：US11508691B2

公开(公告)日：2022-11-22

申请号：US17200931

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00

Abstract: A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.

公开(公告)号：US20220367694A1

公开(公告)日：2022-11-17

申请号：US17330420

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ruey-Chyr Lee

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/40

Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

公开(公告)号：US20220367693A1

公开(公告)日：2022-11-17

申请号：US17396793

申请日：2021-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20220365444A1

公开(公告)日：2022-11-17

申请号：US17348806

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guo-Xin HU ,  Yuh-Kwei CHAO ,  Chung-Yi CHIU

IPC: G03F7/20 ,  G06T7/00 ,  G06K9/46 ,  G06K9/62 ,  G06N20/00

Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.

公开(公告)号：US20220365433A1

公开(公告)日：2022-11-17

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US20220359740A1

公开(公告)日：2022-11-10

申请号：US17335049

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US20220359582A1

公开(公告)日：2022-11-10

申请号：US17333040

申请日：2021-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yu Hsieh

IPC: H01L27/146

Abstract: An image sensor includes a semiconductor substrate, a first isolation structure, a visible light detection structure, and an infrared light detection structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface in a vertical direction. The first isolation structure is disposed in the semiconductor substrate for defining pixel regions in the semiconductor substrate. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region, and a first portion of the visible light detection structure is disposed between the second surface of the semiconductor substrate and the infrared light detection structure in the vertical direction.