公开(公告)号：US20210226050A1

公开(公告)日：2021-07-22

申请号：US17222784

申请日：2021-04-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  H01L27/11 ,  H01L27/11578 ,  G11C16/02 ,  G11C11/404 ,  H01L27/24 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/115

Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

公开(公告)号：US20210193498A1

公开(公告)日：2021-06-24

申请号：US17195628

申请日：2021-03-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, and where at least one of the first transistors controls power delivery to at least one of the second transistors.

公开(公告)号：US11018156B2

公开(公告)日：2021-05-25

申请号：US17099706

申请日：2020-11-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  G11C7/18 ,  H01L27/11565

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.

公开(公告)号：US10998374B1

公开(公告)日：2021-05-04

申请号：US17113045

申请日：2020-12-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146 ,  H01L27/15 ,  H01L25/075 ,  H01L33/62 ,  H01L33/38

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.

公开(公告)号：US10978501B1

公开(公告)日：2021-04-13

申请号：US17121726

申请日：2020-12-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L21/762 ,  H01L23/00 ,  H01L21/84 ,  H01L25/16 ,  H01L25/065 ,  G02B6/12 ,  H01L33/06 ,  G02F1/017

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US10950581B2

公开(公告)日：2021-03-16

申请号：US17065424

申请日：2020-10-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L25/00

Abstract: A 3D semiconductor device including: a first level including a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon, where the second layer includes radio frequency type circuits.

公开(公告)号：US10833108B2

公开(公告)日：2020-11-10

申请号：US16860027

申请日：2020-04-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146 ,  H01L27/15 ,  H01L27/12 ,  H01L27/28

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer is on top of the first single crystal layer, where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the 3D micro display includes an oxide to oxide bonding structure.

公开(公告)号：US10825779B2

公开(公告)日：2020-11-03

申请号：US16907234

申请日：2020-06-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/02 ,  H01L21/00 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

公开(公告)号：US10651054B2

公开(公告)日：2020-05-12

申请号：US16115519

申请日：2018-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/498 ,  H01L27/092 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522 ,  H01L23/367 ,  H01L25/00 ,  H01L27/098 ,  H01L23/373 ,  H01L23/50 ,  H01L21/8238

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

公开(公告)号：US10418369B2

公开(公告)日：2019-09-17

申请号：US15990611

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/112 ,  H01L27/11556 ,  H01L23/48 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/02 ,  G11C13/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C17/16 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/24

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.