公开(公告)号：US20220365725A1

公开(公告)日：2022-11-17

申请号：US17741403

申请日：2022-05-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Ignatowski ,  Valentina Salapura ,  Ganesh Dasika ,  Gabriel H Loh

IPC: G06F3/06

Abstract: A method includes receiving from a compute element a command for performing a requested operation on data stored in a memory device, and in response to receiving the command, performing the requested operation by generating a plurality of memory access requests based on the command and issuing the plurality of memory access requests to the memory device.

公开(公告)号：US11500778B2

公开(公告)日：2022-11-15

申请号：US16813075

申请日：2020-03-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  James Michael O'Connor ,  Michael Mantor

IPC: G06F12/0862 ,  G06F9/52 ,  G06F8/41

Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel with reduced intermediate state storage resource requirements. These include executing a prefetch kernel on a graphics processing unit (GPU), such that the prefetch kernel begins executing before a processing kernel. The prefetch kernel performs memory operations that are based upon at least a subset of memory operations in the processing kernel.

公开(公告)号：US20220358996A1

公开(公告)日：2022-11-10

申请号：US17359254

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/10

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

公开(公告)号：US11496241B2

公开(公告)日：2022-11-08

申请号：US17219198

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Seyedmohammad Seyedzadehdelcheh

IPC: H04L1/18 ,  H04L1/00 ,  H03M13/25 ,  H03M13/11

Abstract: Data transmission mitigating interwire crosstalk including: dividing a data block to be transmitted from a transmitter to a receiver across a set of signal wires into sub-blocks; encoding each of the sub-blocks into a plurality of codewords; selecting, for each sub-block by a cost function, one of the codewords that is less likely to introduce interwire crosstalk; transmitting the selected codewords; and updating the cost function at the transmitter with feedback from the receiver.

公开(公告)号：US11494316B2

公开(公告)日：2022-11-08

申请号：US17085304

申请日：2020-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Brendan T. Mangan

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1009

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US11494211B2

公开(公告)日：2022-11-08

申请号：US16390663

申请日：2019-04-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F9/455 ,  G06F12/1009

Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.

公开(公告)号：US11494087B2

公开(公告)日：2022-11-08

申请号：US16175926

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Georgios Mappouras ,  Amin Farmahini Farahani ,  Michael Ignatowski

IPC: G06F3/06

Abstract: Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

公开(公告)号：US11487447B2

公开(公告)日：2022-11-01

申请号：US17006646

申请日：2020-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

公开(公告)号：US11481953B2

公开(公告)日：2022-10-25

申请号：US16424430

申请日：2019-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Rohan Mehalwal

IPC: G06T15/50 ,  G06T15/06 ,  G06F9/30 ,  G06T15/00

Abstract: Described herein are techniques for performing ray tracing operations. A command processor executes custom instructions for orchestrating a ray tracing pipeline. The custom instructions cause the command processor to perform a series of loop iterations, each at a particular recursion depth. In a first loop iteration, a ray generation shader is executed that triggers execution of a trace ray operation. In any other iteration, zero or more shaders are executed based on the contents of a shader queue. Any shader may trigger execution of a trace ray operation. The trace ray operation determines whether a ray specified by the shader intersects a triangle. The ray trace operation places shader entries into a shader queue, at the current recursion depth plus 1. The command processor updates the current recursion depth based on whether a trace ray operation is executed. The loop ends when the recursion depth is less than a threshold.

公开(公告)号：US11481250B2

公开(公告)日：2022-10-25

申请号：US16024244

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Matthew David Sinclair ,  Bradford Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.