公开(公告)号：US11552707B2

公开(公告)日：2023-01-10

申请号：US17302681

申请日：2021-05-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mir Ashkan Seyedi ,  Terrel Morris

IPC: H04J14/00 ,  H04B10/275 ,  H04B10/40

Abstract: An optical transceiver module includes an optical transceiver and a controller. The optical transceiver has a ring filter configured to transmit optical signals from or receive optical signals for the optical transceiver module. The controller is configured to: detect a carrier frequency at the optical transceiver; detect a data signal frequency of data at the optical transceiver; determine a bit error rate of the data; and in response to determining that the bit error rate of the data is greater than a threshold, periodically vary a central wavelength of the ring filter at a frequency at least three orders slower than the data signal frequency.

公开(公告)号：US11546856B2

公开(公告)日：2023-01-03

申请号：US17071585

申请日：2020-10-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Charles Lukaszewski ,  Sachin Ganu ,  Shahnawaz Siraj ,  Eldad Perahia ,  Andre Beaudin ,  Qiang Zhou

IPC: H04W52/02 ,  H04L12/24 ,  H04L41/052 ,  H04L41/0246

Abstract: Examples provided herein describe a method for managing power consumption of a network. For example, a network device may monitor a set of network area zones of a network coverage area, where each network area zone is associated with a set of edge devices. A first occupancy state may be determined for a first network area zone of the set of network area zones based on usage of a first set of edge devices of the first network area zone. Based on the determined first occupancy state, a first power consumption policy for the first network area zone may be determined. Responsive to determining the first power consumption policy, the determined first power consumption policy may be applied to the first set of edge devices in the first network area zone at least edge changing a power consumption mode of a first edge device in the first set of edge devices.

公开(公告)号：US11546328B2

公开(公告)日：2023-01-03

申请号：US16255937

申请日：2019-01-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Rafael Anton Eichelberger ,  Carlos Gomez Gallego ,  Sebastien Tandel ,  Juliano Cardoso Vacaro

IPC: H04L29/06 ,  H04L9/40 ,  H04L67/12

Abstract: A device is authenticated for communication over a network based on a sensor data signature and a traffic pattern signature. The sensor data signature and the traffic pattern signature identify the device. A determination is made whether the sensor data signature corresponds to one of a plurality of recognized sensor data signatures. A determination is also made whether the traffic pattern signature of the device corresponds to one of a plurality of recognized traffic pattern signatures. The device is authenticated for communication over the network responsive to determining that the sensor data signature corresponds to one of the plurality of recognized sensor data signatures and the traffic pattern signature corresponds to one of the plurality of recognized traffic pattern signatures.

公开(公告)号：US11546024B2

公开(公告)日：2023-01-03

申请号：US17353876

申请日：2021-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amogh Guruprasad Deshmukh ,  Eldad Perahia ,  Sachin Ganu

IPC: H04B7/0452 ,  H04B7/0417 ,  H04W72/04 ,  H04B7/0456

Abstract: Systems and methods are provided for optimizing channel bandwidth while increasing downlink multi-user, multiple-input, multiple-output (DL MU-MIMO) gain. Depending on the access point (AP) platform, for example, APs exhibit certain characteristics regarding DL MU-MIMO gain as a function of the number of DL MU-MIMO clients associated to the AP. Accordingly, APs can be configured to operate in accordance with an algorithm that checks the number of DL MU-MIMO capable clients are associated to an AP, and dynamically switch between single- and dual-radio modes of operation to take advantage of those DL MU-MIMO gains.

公开(公告)号：US11544540B2

公开(公告)日：2023-01-03

申请号：US16409729

申请日：2019-05-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Sergey Serebryakov

IPC: G06N3/08 ,  G11C7/10 ,  G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Systems and methods are provided for implementing hardware optimization for a hardware accelerator. The hardware accelerator emulates a neural network. Training of the neural network integrates a regularized pruning technique to systematically reduce a number of weights. A crossbar array included in hardware accelerator can be programmed to calculate node values of the pruned neural network to selectively reduce the number of weight column lines in the crossbar array. During deployment, the hardware accelerator can be programmed to power off periphery circuit elements that correspond to a pruned weight column line to optimize the hardware accelerator for power. Alternatively, before deployment, the hardware accelerator can be optimized for area by including a finite number of weight column line. Then, regularized pruning of the neural network selectively reduces the number of weights for consistency with the finite number of weight columns lines in the hardware accelerator.

公开(公告)号：US20220413741A1

公开(公告)日：2022-12-29

申请号：US17359080

申请日：2021-06-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Yann Livis ,  Dmitry L. Ivanov ,  Oleg Neverovitch

IPC: G06F3/06

Abstract: A system divides non-volatile memory of a plurality of storage devices into physical extents which comprises chunks. The system allocates slabs associated with the storage devices, wherein a respective slab comprises extents from different storage devices and further comprises stripes. A stripe comprises a chunk from each extent of the respective slab. The system updates, in a first data structure, an entry which indicates: a slab number for the respective allocated slab; and a storage device identifier and an extent number for each extent in the respective allocated slab. Responsive to receiving a write request, the system obtains a first stripe from a pre-allocated list which includes the allocated slabs. The system searches, based on stripe information associated with the first stripe, the first data structure to obtain a physical location in a storage device to which to issue the write request.

公开(公告)号：US11536402B2

公开(公告)日：2022-12-27

申请号：US16579254

申请日：2019-09-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Franz ,  Tahir Cader

IPC: F16L21/035 ,  F16L21/03 ,  H05K7/20

Abstract: Hose barb fittings and apparatuses described herein provide increased fluid-flow rates for cooling loops used for thermal control in computer system. A hose barb fitting comprises a fluid-flow passage that extends through the hose barb fitting from a first opening to a second opening. The ratio of the cross-sectional area of the fluid-flow passage to the cross-sectional area of the hose barb fitting is between 0.4 and 0.7, inclusive. When the hose barb fitting is fully seated within a housing structure, a specialized gasket acts as both a radial seal and a face seal. Also, a flange extending from the housing structure engages with a flange extending from the hose barb fitting to prevent the hose barb fitting from being unseated.

公开(公告)号：US20220407810A1

公开(公告)日：2022-12-22

申请号：US17354584

申请日：2021-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Diego Dompe ,  Laura Salazar ,  Jose Luis Uribe

IPC: H04L12/851 ,  H04L12/803

Abstract: One aspect provides a network switch. The network switch includes hardware-based packet-processing logic for processing received packets, a processing unit, and an offload engine coupled to the processing unit. The offload engine is to offload, from the processing unit, packet-processing operations associated with a subset of the received packets. The offload engine comprises a processor core, at least one hardware packet-processing accelerator for performing the packet-processing operations, and a function-helper logic for interfacing between the processor core and the hardware packet-processing accelerator.

公开(公告)号：US20220405006A1

公开(公告)日：2022-12-22

申请号：US17355000

申请日：2021-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dmitry L. Ivanov ,  Yann Livis ,  Oleg Neverovitch

IPC: G06F3/06

Abstract: One aspect facilitates a global map in a distributed system. The system generates a first data structure which comprises key-value pairs, wherein, in a respective key-value pair, the respective key is an integer and the respective value comprises a pointer to a sparse array which includes a bitmap (such as an ordered two-bit bitmap). The system stores the first data structure as a first partition of the global map. The system searches, based on a pattern, the first data structure to obtain a first value. If the first value comprises a two-bit bitmap, the system converts, based on the pattern, the first value to a two-dimensional bitmap, and performs a function on the first value to obtain a first result. The system uses the first value or the first result as metadata to execute a read or write operation in a filesystem associated with the distributed system.

公开(公告)号：US11532356B2

公开(公告)日：2022-12-20

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.