公开(公告)号：US20140111494A1

公开(公告)日：2014-04-24

申请号：US14048013

申请日：2013-10-07

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chia-Wei Su ,  Po-Yu Tseng ,  Shun-Hsun Yang ,  Po-Hsiang Fang

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G2310/0248 ,  G09G2330/023

Abstract: A self-detection charge sharing module for a liquid crystal display device is disclosed. The self-detection charge sharing module includes at least one detecting unit, for detecting a plurality of input voltages of a plurality of operational amplifiers driving a plurality of data line sand a plurality of output voltage of the plurality of data line, to generate at least one detecting result, and at least one charge sharing unit, for conducting connection between at least one first data line and at least one second data line among the plurality of data line when the at least one detecting result indicates at least one corresponding first input voltage and at least one corresponding second input voltage among the plurality of input voltage have opposite voltage variation direction and vary toward each other. The at least one first input voltage and the at least one second input voltage maintain respective polarities.

Abstract translation: 公开了一种用于液晶显示装置的自检电荷共享模块。 自检电荷共享模块包括至少一个检测单元，用于检测多个运算放大器的多个输入电压，该多个运算放大器驱动多条数据线砂多个数据线的多个输出电压，至少产生 一个检测结果和至少一个电荷共享单元，用于当所述至少一个检测结果指示至少一个对应的第一输入电压时，在所述多个数据线中的至少一个第一数据线和至少一个第二数据线之间进行连接 并且所述多个输入电压中的至少一个对应的第二输入电压具有相反的电压变化方向并且彼此变化。 所述至少一个第一输入电压和所述至少一个第二输入电压维持相应的极性。

公开(公告)号：US20140097871A1

公开(公告)日：2014-04-10

申请号：US13736967

申请日：2013-01-09

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jer-Hao Hsu

IPC: G01R19/10

CPC classification number: G01R19/10 ,  H03K5/2481

Abstract: A latch comparator device includes a differential input amplifier coupled between a first system voltage and a second system voltage and including a first differential output signal terminal and a second differential output signal terminal, a latch coupled to a third system voltage including a first latch signal terminal and a second latch signal terminal, a switch module including a first switch device and a second switch device, wherein the first switch device is coupled between the first differential output signal terminal and the second latch signal terminal and the second switch device is coupled between the second differential output signal terminal and the first latch signal terminal, and a third switch device is coupled between the latch and a fourth system voltage.

Abstract translation: 锁存比较器装置包括耦合在第一系统电压和第二系统电压之间并包括第一差分输出信号端和第二差分输出信号端的差分输入放大器，耦合到第三系统电压的锁存器，包括第一锁存信号端 以及第二锁存信号端子，包括第一开关装置和第二开关装置的开关模块，其中所述第一开关装置耦合在所述第一差分输出信号端子和所述第二锁存信号端子之间，并且所述第二开关装置耦合在所述第一开关装置 第二差分输出信号端子和第一锁存信号端子，以及第三开关器件耦合在锁存器和第四系统电压之间。

公开(公告)号：US20140097802A1

公开(公告)日：2014-04-10

申请号：US13772330

申请日：2013-02-21

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Wing-Kai Tang ,  Cheng-Wen Chang

IPC: H02J15/00

CPC classification number: H02J15/00 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0291

Abstract: The present invention discloses a charging system for charging a capacitor. The charge system includes at least one unit gain buffer, driven by a plurality of driving voltages, each unit gain buffer having a positive input terminal for receiving a target voltage and a negative input terminal coupled to an output terminal, a plurality of switches coupled between the plurality of driving voltages and the capacitor, and a switch control waveform generator, coupled to the plurality of switches, for switching on one of the for a specific driving voltage among the plurality of driving voltages to drive one of the at least one unit gain buffer to charge the capacitor.

Abstract translation: 本发明公开了一种用于对电容器充电的充电系统。 所述充电系统包括由多个驱动电压驱动的至少一个单位增益缓冲器，每个单位增益缓冲器具有用于接收目标电压的正输入端子和耦合到输出端子的负输入端子，多个开关耦合在 所述多个驱动电压和所述电容器以及耦合到所述多个开关的开关控制波形发生器，用于接通所述多个驱动电压中的特定驱动电压中的一个以驱动所述至少一个单位增益中的一个 缓冲器为电容器充电。

公开(公告)号：US08681086B2

公开(公告)日：2014-03-25

申请号：US13722326

申请日：2012-12-20

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Hsun Peng ,  Hsi-Chi Ho ,  Li-Chun Huang

IPC: G09G3/36

CPC classification number: G09G5/00 ,  G09G3/3688 ,  G09G2310/0289 ,  G09G2310/0297

Abstract: A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on.

Abstract translation: 数据驱动器包括用于分别根据第一和第二像素数据提供正和负像素电压的两个数据处理电路，以及包括多路复用器单元的多路复用器电路。 每个多路复用器单元具有分别接收正像素电压和负像素电压的第一和第二输入端子以及耦合到数据线的输出端子。 第一开关装置具有串联耦合在第一输入端和输出端之间的第一和第二开关。 第一和第二开关之间的节点经由第三开关选择性接地。 第二开关器件具有串联耦合在第二输入和输出端子之间的第四和第五开关。 第四开关和第五开关之间的节点通过第六开关选择性接地。 当第一和第二开关导通时，第六开关导通。 当第四和第五开关导通时，第三开关导通。

公开(公告)号：US20140071106A1

公开(公告)日：2014-03-13

申请号：US13677314

申请日：2012-11-15

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jr-Ching Lin ,  Hsin-Hung Lee ,  Chia-Wei Su ,  Po-Yu Tseng ,  Shun-Hsun Yang ,  Po-Hsiang Fang

IPC: G09G1/00

CPC classification number: G09G3/3696 ,  G09G1/005 ,  G09G3/3688 ,  G09G2320/0673

Abstract: A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data from the timing controller via a data bus, converts the first pixel data to a first drive voltage according to a first reference voltage group, and drives a display panel by the first drive voltage. The voltage controller receives a voltage command from the timing controller, generates and changes a first reference voltage configuration data according to the voltage command. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data to generate and adjust the first reference voltage group for applying to the first drive channel circuit. Furthermore, a method for updating a new gamma curve by the source driver is also provided.

Abstract translation: 源驱动器包括第一驱动通道电路，电压控制器和第一可编程电压缓冲器单元。 第一驱动通道电路经由数据总线从定时控制器接收第一像素数据，根据第一参考电压组将第一像素数据转换为第一驱动电压，并且通过第一驱动电压驱动显示面板。 电压控制器从定时控制器接收电压指令，根据电压指令产生并改变第一参考电压配置数据。 第一可编程电压缓冲器单元耦合到电压控制器和第一驱动通道电路，并且接收第一参考电压配置数据以产生和调整第一参考电压组以施加到第一驱动通道电路。 此外，还提供了用于由源驱动器更新新伽玛曲线的方法。

公开(公告)号：US20140062556A1

公开(公告)日：2014-03-06

申请号：US13670466

申请日：2012-11-07

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Yi-Kuang Chen

IPC: H03L7/24 ,  H03L7/00

CPC classification number: H03K23/40 ,  H03K23/68

Abstract: A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

Abstract translation: 多相时钟分频器包括：用于产生多个参考时钟的参考时钟发生器; 以及至少一个输出时钟发生器，包括用于选择输出所选择的参考时钟的第一多路复用器，用于选择输出第一选择的输入时钟的第二多路复用器，用于选择输出第二选择的输入时钟的第三多路复用器， 触发器，用于根据所选择的参考时钟和第一选择的输入时钟输出第一采样时钟;第二触发器，用于根据第一采样时钟和第二选择的输入时钟输出第二采样时钟;以及第四多路复用器，用于选择 以输出第一采样时钟或第二采样时钟以产生输出时钟。

公开(公告)号：US20140042917A1

公开(公告)日：2014-02-13

申请号：US14058951

申请日：2013-10-21

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Hsing-Chien YANG ,  Wen-Hsin Cheng ,  Ying-Hao Hsu ,  Lan-Ting Hsu ,  Tsung-Hau Chang

IPC: H05B33/08

CPC classification number: H05B33/0806 ,  H05B33/0818 ,  H05B33/0845

Abstract: A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal.

Abstract translation: 发光二极管（LED）驱动电路包括LED控制电路和功率级电路。 LED控制电路在频域中将输入脉宽调制（PWM）信号向较高频率方向移位，以产生具有与输入PWM信号的占空比基本相同的占空比的输出PWM信号。 功率级电路根据输出PWM信号输出LED驱动电流。

公开(公告)号：US20140042300A1

公开(公告)日：2014-02-13

申请号：US13684253

申请日：2012-11-23

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jer-Hao Hsu

IPC: H03M1/12 ,  H01L27/146

CPC classification number: H03M1/124 ,  H01L27/146 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

Abstract: An image sensor and a column analog-to-digital converter thereof are provided. The column analog-to-digital converter includes a counter providing a counter result, a ramp signal generator providing a ramp signal and a start signal, a sampling and comparing array, a first latch array, a second latch array, and an arithmetic unit. The sampling and comparing array outputs a plurality of brightness transformation signals according to the ramp signal, the start signal, and initial voltages and brightness voltages of a plurality of photosensitive pixels. The first and the second latch arrays latch the counter result in response to the brightness transformation signals and output a plurality of first brightness latch values during a first period and a plurality of second brightness latch values during a second period. The arithmetic unit calculates the brightness values of the photosensitive pixels according to the first brightness latch values and the second brightness latch values.

Abstract translation: 提供了图像传感器及其列模数转换器。 列模数转换器包括提供计数器结果的计数器，提供斜坡信号和起始信号的斜坡信号发生器，采样和比较阵列，第一锁存器阵列，第二锁存器阵列和运算单元。 采样和比较阵列根据斜坡信号，起始信号和多个光敏像素的初始电压和亮度电压输出多个亮度变换信号。 第一和第二锁存器阵列响应于亮度变换信号锁存计数器结果，并且在第一周期期间输出多个第一亮度锁存值，并且在第二周期期间输出多个第二亮度锁存值。 算术单元根据第一亮度锁存值和第二亮度锁存值来计算光敏像素的亮度值。

公开(公告)号：US20140015587A1

公开(公告)日：2014-01-16

申请号：US13792245

申请日：2013-03-11

Applicant: NOVATEK MICROELECTRONICS CORP

Inventor： Cheng-Hung Chen ,  Ju-Lin Huang ,  Keko-Chun Liang

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356182

Abstract: A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability.

Abstract translation: 具有动态控制的电平移动电路包括动态控制器和电平转换器。 动态控制器输出动态电压和输出数据信号。 由动态控制器控制的电平移位器包括输入信号接收器，输出信号发生器和偏置电流控制器，它们串联在接地电压和高电平电压之间。 输入信号接收器接收动态控制器的输出数据信号，输出信号发生器根据输入数据信号产生电平移位数据信号。 当电平移位数据信号处于不稳定阶段时，当电平移位数据信号处于稳定级并处于第二电流输出能力时，由动态电压控制的偏置电流控制器处于第一电流输出能力。 第一个电流输出能力大于第二个电流输出能力。

公开(公告)号：US20140010276A1

公开(公告)日：2014-01-09

申请号：US13935868

申请日：2013-07-05

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chia-Hao HSU ,  Yu-Hsing CHIANG

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H04L7/0338 ,  H04L25/03006

Abstract: A clock data recovery circuit includes an equalizer, a multi-phase clock generator, a sampling and check unit, a signal edge detection unit and an adjusting unit. The equalizer performs an equalization on an incoming data signal. The multi-phase clock generator generates multiple clock signals and at least one pair of check signals. The sampling and check unit samples the incoming data signal according to the clock signals to obtain a sequence, and checks whether the sequence matches a predetermined pattern. If so, the signal edge detection unit controls the sampling and check unit to detect a transition between values of the sequence two on two based on the pair of check signals to obtain a detection value. The adjusting unit determines whether the transition is too early or too late according to the detection value, and adjusts the equalization on the incoming data signal according to the determination result.

Abstract translation: 时钟数据恢复电路包括均衡器，多相时钟发生器，采样和检查单元，信号边缘检测单元和调整单元。 均衡器对输入数据信号执行均衡。 多相时钟发生器产生多个时钟信号和至少一对校验信号。 采样和检查单元根据时钟信号对输入数据信号进行采样，以获得序列，并检查序列是否匹配预定模式。 如果是，则信号边缘检测单元控制采样和检查单元，以基于一对检查信号来检测序列二的值之间的转换，以获得检测值。 调整单元根据检测值确定转换是否太早或太晚，并且根据确定结果调整输入数据信号上的均衡。