公开(公告)号：US20030026498A1

公开(公告)日：2003-02-06

申请号：US10171793

申请日：2002-06-14

Applicant: STMicroelectronics, S.r.I.

Inventor： Daniele Sirtori ,  Matteo Maravita

IPC: G06K009/40 ,  G06K009/64

CPC classification number: H04N7/012

Abstract: The conversion into a progressive format of digital images organized in half-frames or fields with interlaced lines or rows envisages selecting successive lines in one or more of said fields and reconstructing by pixels an image line set between the interlaced lines selected. The reconstruction operation obtains the image by creating a set of candidate patterns associated to the work window by selecting the patterns to be considered within the window. Next, applying to the patterns of the aforesaid set a first cost function which is representative of the correlations between pairs of pixels. Applying to the patterns of the aforesaid set a second cost function which is representative of the non-correlations between pairs of pixels. Selecting, for each candidate pattern, respective internal correlations and external non-correlations, calculating corresponding scores for the candidate patterns using the aforesaid first cost function. Selecting a best pattern by comparing the respective scores of the candidate patterns with at least one threshold; and selecting the pixels of the window identified by the best pattern selected, then reconstructing the missing line by filtration starting from said pixels.

Abstract translation: 以半帧或具有交错行或行的场的数字图像的逐行格式的转换设想在一个或多个所述场中选择连续的行，并且通过像素重建在所选择的交织行之间设置的图像行。 重建操作通过选择在窗口内考虑的模式来创建与工作窗口相关联的一组候选模式来获得图像。 接下来，应用上述的图案设置表示像素对之间的相关性的第一成本函数。 应用上述的图案设置表示像素对之间的非相关性的第二成本函数。 对于每个候选模式，选择各自的内部相关性和外部非相关性，使用前述第一成本函数计算候选模式的相应分数。 通过将候选模式的各个分数与至少一个阈值进行比较来选择最佳模式; 并选择由所选择的最佳图案标识的窗口的像素，然后从所述像素开始重新构建缺失的线。

公开(公告)号：US20030018861A1

公开(公告)日：2003-01-23

申请号：US10159782

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC: G06F012/00

CPC classification number: G06F11/1072 ,  G11C2211/5641

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Abstract translation: 一种用于存储可配置位数的多电平存储单元中的误差控制的方法。 使用在编码阶段中对由r位数据的k个符号组成的b位二进制字符串进行操作的错误控制代码执行错误控制。 当存储器单元存储数位r的位时，仅与存储在存储单元中的数据位形成数据符号。 当存储器单元存储少于r的位数时，形成数据符号，其中存储在存储单元中的数据位和具有预定逻辑值的rs位，其中存储在存储单元中的数据位 被布置在数据符号的最低有效部分中，并且具有预定逻辑值的rs位被布置在数据符号的最重要部分中。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

公开(公告)号：US20020186592A1

公开(公告)日：2002-12-12

申请号：US10118660

申请日：2002-04-08

Applicant: STMicroelectronics S.r.I.

Inventor： Mauro Pagliato ,  Paolo Rolandi ,  Massimo Montanaro

IPC: G11C011/34

CPC classification number: G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

Abstract: Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

Abstract translation: 这里描述的是一种异步串行二点读出放大器，它包括第一比较器级，该第一比较器级具有接收在多级存储器单元中流动的单元电流的第一输入，其内容将被读取，接收第一参考电流的第二输入和输出 提供存储在多层存储单元中的第一位; 多路复用器级，其具有连接到第一比较器级的输出的选择输入，接收第二参考电流的第一信号输入，接收第三参考电流的第二信号输入和可选地可连接到第一或第二信号的信号 输入取决于选择输入上存在的逻辑电平; 以及第二比较器级，其具有接收单元电流的第一输入，连接到多路复用器级的信号输出的第二输入和提供存储在多电平存储单元中的第二位的输出。

公开(公告)号：US20020159528A1

公开(公告)日：2002-10-31

申请号：US10072818

申请日：2002-02-08

Applicant: STMicroelectronics, S.r.I.

Inventor： Andrea Graziani ,  Luca Celetto ,  Daniele Alfonso ,  Fabrizio Basso ,  Alessandro Cremonesi ,  Danilo Pau

IPC: H04N007/12

CPC classification number: H04N19/40 ,  H04N19/90

Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.

Abstract translation: 为了从输入MPEG比特流开始，输出MPEG比特流，其具有相对于输入比特流修改的语法，分辨率和比特率中选择的至少一个实体，在输入比特流中区分第一部分和第二部分，其中 分别基本上不影响并确实影响比特率的变化。 当要修改语法和分辨率之间的至少一个时，输入比特流的第一部分经受所需的翻译，然后将经过语法和/或分辨率转换的所述第一部分传送到输出比特流。 当分辨率保持不变时，在实质上没有处理操作的情况下，第二部分从输入比特流传送到输出比特流。 当分辨率改变时，输入比特流的第二部分在离散余弦变换的域中进行滤波。

公开(公告)号：US20020141241A1

公开(公告)日：2002-10-03

申请号：US10068565

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I.

Inventor： Irene Babudri ,  Mauro Giacomini

IPC: G11C016/26

CPC classification number: G11C29/24 ,  G11C16/28

Abstract: A memory device implements a reading operation that comprises: providing first and second additional memory cells whose threshold voltage values correspond to a maximum value and a minimum value of a distribution of threshold voltages of a cell array of the memory device; programming the first and second additional memory cells with predetermined first and second logic values; simultaneously reading a logic contents of the first and second additional memory cells, and data to be read in the cell array; comparing the logic contents of the first and second additional memory cells, as read during the reading step, with the first and second predetermined logic values; generating a result signal of the comparison step, such a result signal having a first value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, matching the first and second predetermined logic values, respectively, and having a second value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, failing to match the first and second predetermined logic values, respectively.

Abstract translation: 存储器件实现读取操作，其包括：提供其阈值电压值对应于存储器件的单元阵列的阈值电压分布的最大值和最小值的第一和第二附加存储器单元; 以预定的第一和第二逻辑值对第一和第二附加存储器单元进行编程; 同时读取第一和第二附加存储器单元的逻辑内容以及要在单元阵列中读取的数据; 将在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容与第一和第二预定逻辑值进行比较; 生成比较步骤的结果信号，在读取步骤期间读取第一和第二附加存储器单元的逻辑内容的情况下具有第一值的结果信号分别与第一和第二预定逻辑值相匹配 并且在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容的第二值分别不匹配第一和第二预定逻辑值。

公开(公告)号：US20020094665A1

公开(公告)日：2002-07-18

申请号：US10068108

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I

Inventor： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Montanini

IPC: H01L021/20

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

Abstract: Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Abstract translation: SOI晶片的制造方法。 在单晶硅晶片上，形成由抗氧化材料制成的具有翻转U形状的保护区域，保护区域覆盖第一晶片部分。 在晶片中形成深沟槽，其在第一晶片部分之间延伸并横向限定第一晶片部分，除了被保护区域覆盖的上部区域之外，完全氧化第一晶片部分，以形成至少一个覆盖氧化物的连续区域， 氧化上部。 去除保护区域，并从非氧化的上部部分外延生长结晶半导体材料层。

公开(公告)号：US20020089317A1

公开(公告)日：2002-07-11

申请号：US10008540

申请日：2001-11-07

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Ilaria Motta ,  Rino Micheloni ,  Guido Torelli

IPC: G05F001/40

CPC classification number: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract translation: 一种电压调节器，具有比较器，输出端子是调节器的输出端子，用于连接到电压源的端子，连接到比较器的输入端子的参考电压源，以及连接在输出端子之间的反馈电路 和比较器的另一个输入端。 为了防止从待机状态转换到活动状态的瞬变，提供了提供基本上等于第一源的参考电压的第二参考电压源，用于将第二源连接到另一个输入端的开关 的控制电路，以及控制电路，其能够启动调节器的供应并且可以在调节器的供应被激活时将开关闭合预定的一段时间。

公开(公告)号：US20020067640A1

公开(公告)日：2002-06-06

申请号：US09972769

申请日：2001-10-05

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C016/04

CPC classification number: G11C7/1042 ,  G11C8/12 ,  G11C16/08

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract translation: 一种半导体存储器架构，其具有两个存储体，每个存储体各自包含相应的存储器位置，并且对于每个存储体，各个电路用于选择存储体的位置以及用于读取包含在存储体的选定位置中的数据的相应电路，转移结构 由与存储体相关联的读取电路读取的数据读取到存储器的数据输出端，存在一次分配给一个存储体的单个数据传输结构，其中包括存储用于存储最近的数据读取的存储器 读取电路和输出驱动器电路被选择性地激活，以将寄存器的内容传送到存储器的数据输出端，对于每个存储体，具有用于存储器位置的顺序扫描的寻址结构 ，可操作地连接到相应的电路以选择存储体的位置。

公开(公告)号：US20020063573A1

公开(公告)日：2002-05-30

申请号：US09948144

申请日：2001-09-06

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Genova ,  Roberto Gariboldi ,  Aldo Novelli ,  Giulio Ricotti

IPC: G01R031/26

CPC classification number: G01R19/16519 ,  H02M2001/0009

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract translation: 该装置和方法通过包括检测晶体管的功率晶体管来监测传送到负载的电流。 该电路包括具有差分级的干扰衰减电路，以及参考地的第一，第二和第三级，其各个输入节点共同连接到差分级的输出节点。 第三级由与第一级的晶体管相同的晶体管形成，并将电流信号通过其电流端与传递给负载的电流成比例。