公开(公告)号：US20220262808A1

公开(公告)日：2022-08-18

申请号：US17706577

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20220262806A1

公开(公告)日：2022-08-18

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11417564B2

公开(公告)日：2022-08-16

申请号：US17190439

申请日：2021-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure dividing the fin-shaped structure into a first portion and a second portion as the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion, a spacer around the top portion, a first epitaxial layer adjacent to one side of the top portion, and a second epitaxial layer adjacent to another side of the top portion.

公开(公告)号：US11411009B2

公开(公告)日：2022-08-09

申请号：US16828966

申请日：2020-03-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wen-Fu Huang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.

公开(公告)号：US20220238800A1

公开(公告)日：2022-07-28

申请号：US17180876

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20220238793A1

公开(公告)日：2022-07-28

申请号：US17183292

申请日：2021-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor device includes a synthetic antiferromagnetic (SAF) layer on a substrate, a barrier layer on the SAF layer, and a free layer on the barrier layer. Preferably, the SAF layer further includes a first pinned layer, a first spacer on the first pinned layer, a second pinned layer on the first spacer, a second spacer on the second pinned layer, and a reference layer on the second spacer.

公开(公告)号：US20220238600A1

公开(公告)日：2022-07-28

申请号：US17717127

申请日：2022-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lee ,  I-Ming Tseng ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.

公开(公告)号：US20220238468A1

公开(公告)日：2022-07-28

申请号：US17159080

申请日：2021-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US20220230975A1

公开(公告)日：2022-07-21

申请号：US17715067

申请日：2022-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Wen-Shen Li ,  Ching-Yang Wen

IPC: H01L23/66 ,  H01L21/762 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

公开(公告)号：US20220223710A1

公开(公告)日：2022-07-14

申请号：US17709385

申请日：2022-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.