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    Secure computer vision processing
    31.
    发明授权
    Secure computer vision processing 有权

    公开(公告)号：US12045362B2

    公开(公告)日：2024-07-23

    申请号：US17889956

    申请日：2022-08-17

    Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

    Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Tung Chuen Kwong ,  Guhan Krishnan

    IPC: G06F21/62 ,  G06V10/94

    CPC classification number: G06F21/6218 ,  G06V10/955

    Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

    SHARED CURRENT SENSING UNIT
    33.
    发明公开
    SHARED CURRENT SENSING UNIT 审中-公开

    公开(公告)号：US20240235233A1

    公开(公告)日：2024-07-11

    申请号：US18405800

    申请日：2024-01-05

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： David King Wai Li ,  Amanullah Samit

    IPC: H02J7/00 ,  G01R31/382

    CPC classification number: H02J7/0068 ,  G01R31/382 ,  H02J2207/20

    Abstract: A device is disclosed that includes a battery charge controller having an input removably connected to a power adapter and an output supplying DC current to a battery, a voltage regulator having an input coupled to the output of the battery charge controller and the battery, and a current sensing unit used by the battery charge controller for sensing a charging current to the battery and by the voltage regulator for sensing a discharging current from the battery. Various other methods and systems are also disclosed.

    WRONG WAY READ-BEFORE WRITE SOLUTIONS IN SRAM
    35.
    发明公开
    WRONG WAY READ-BEFORE WRITE SOLUTIONS IN SRAM 审中-公开

    公开(公告)号：US20240221805A1

    公开(公告)日：2024-07-04

    申请号：US18090736

    申请日：2022-12-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Russell Schreiber ,  Sahilpreet Singh

    IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

    CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/1096

    Abstract: A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.

    LATENCY MEASUREMENT SYSTEM AND METHOD
    37.
    发明公开
    LATENCY MEASUREMENT SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240214283A1

    公开(公告)日：2024-06-27

    申请号：US18088935

    申请日：2022-12-27

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Gennadiy Kolesnik ,  Mikhail Mironov

    IPC: H04N21/438 ,  H04N21/442

    CPC classification number: H04N21/4384 ,  H04N21/44209

    Abstract: A client latency module generates a trigger event in response to an input event. The trigger event is inserted into an event queue to be sent to a content provider system. A stream including a plurality of images, audio data, or both, is received from the content provider system. A trigger event response generated in response to the trigger event is identified from the stream. A stream latency is determined by comparing a time corresponding to the trigger event with a time corresponding to the trigger event response. As a result, a single timer is used to measure latency of a streaming solution.

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