公开(公告)号：US12191186B2

公开(公告)日：2025-01-07

申请号：US18338443

申请日：2023-06-21

Applicant: Applied Materials, Inc.

Inventor： Benjamin B. Riordon ,  James D. Strassner

IPC: H01L21/683 ,  B05C21/00 ,  C23C14/04 ,  C23C16/04 ,  C23C16/458 ,  H01L21/02 ,  H01L21/687

Abstract: Embodiments of the present disclosure are related to carrier assemblies that can clamp more than one optical device substrates and methods for forming the carrier assemblies. The carrier assembly includes a carrier, one or more substrates, and a mask. The carrier is magnetically coupled to the mask to retain the one or more substrates. The carrier assembly is used for supporting and transporting the one or more substrates during processing. The carrier assembly is also used for masking the one or more substrates during PVD processing. Methods for assembling the carrier assembly in a build chamber are described herein.

公开(公告)号：US12190994B2

公开(公告)日：2025-01-07

申请号：US18090574

申请日：2022-12-29

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Mahendrakumar Gunasekaran ,  Mohammad Anees

IPC: G11C7/22 ,  G11C7/10

Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

公开(公告)号：US12190077B2

公开(公告)日：2025-01-07

申请号：US17993464

申请日：2022-11-23

Applicant: XILINX, INC.

Inventor： Sai Ram Venkata Pattabhi Nedunuri ,  Killivalavan Kaliyamoorthy

IPC: G06F5/06 ,  G06F1/10 ,  H04L25/02

Abstract: A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data. The aligner circuit outputs the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit. The aligner circuit outputs the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.

公开(公告)号：US12189049B2

公开(公告)日：2025-01-07

申请号：US17461516

申请日：2021-08-30

Applicant: QUALCOMM Incorporated

Inventor： Jamie Menjay Lin ,  Nojun Kwak ,  Fatih Murat Porikli

IPC: G01S5/02 ,  G06N20/00 ,  H04W4/029

Abstract: Certain aspects of the present disclosure provide techniques for machine learning using basis decomposition, comprising receiving a first runtime record, where the first runtime record includes RF signal data collected in a physical space; processing the first runtime record using a plurality of basis machine learning (ML) models to generate a plurality of inferences; aggregating the plurality of inferences to generate a prediction comprising a plurality of coordinates; and outputting the prediction, where the plurality of coordinates indicate a location of a physical element in a physical space.

公开(公告)号：US12186832B2

公开(公告)日：2025-01-07

申请号：US17203239

申请日：2021-03-16

Applicant: Applied Materials, Inc.

Inventor： Stephen Moffatt ,  Joseph M. Ranish

IPC: B23K26/352 ,  B23K26/00 ,  B23K26/0622 ,  B23K26/08 ,  B23K26/12 ,  B23K26/354 ,  B23K103/00 ,  F27B5/18 ,  F27D19/00 ,  F27D21/00 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/67 ,  F27B5/14

Abstract: The present invention generally describes apparatuses and methods used to perform an annealing process on desired regions of a substrate. In one embodiment, pulses of electromagnetic energy are delivered to a substrate using a flash lamp or laser apparatus. The pulses may be from about 1 nsec to about 10 msec long, and each pulse has less energy than that required to melt the substrate material. The interval between pulses is generally long enough to allow the energy imparted by each pulse to dissipate completely. Thus, each pulse completes a micro-anneal cycle. The pulses may be delivered to the entire substrate at once, or to portions of the substrate at a time. Further embodiments provide an apparatus for powering a radiation assembly, and apparatuses for detecting the effect of pulses on a substrate.

公开(公告)号：USD1055764S1

公开(公告)日：2024-12-31

申请号：US29861586

申请日：2022-11-30

Applicant: Alexander Dennis Limited

Designer： Simon Bishop ,  Michael Todd ,  Jamie Wilson ,  David Louch ,  Kirit Patel

公开(公告)号：US12184433B2

公开(公告)日：2024-12-31

申请号：US17755216

申请日：2019-10-25

Applicant: QUALCOMM Incorporated

Inventor： Hui Guo ,  Sudhir Kumar Baghel ,  Kapil Gulati ,  Tien Viet Nguyen ,  Shuanshuan Wu ,  Gabi Sarkis

IPC: H04L1/1867 ,  H04L1/1812 ,  H04L1/1829 ,  H04W72/21 ,  H04W72/23

Abstract: Certain aspects of the present disclosure provide techniques for multiplexing HARQ feedback in a same slot for downlink and sidelink transmissions. An example method generally includes receiving, from a network entity, a downlink control information (DCI) that schedules resources for at least one physical sidelink shared channel (PSSCH) transmission from the first UE to a second UE, transmitting data to the second UE via the at least one PSSCH transmission using the scheduled resources, receiving, from the second UE, acknowledgment feedback for the at least one PSSCH transmission, selecting at least one codebook entry for providing feedback for at least one downlink transmission from the network entity to the first UE and the acknowledgment feedback for the at least one PSSCH transmission in a same physical uplink control channel (PUCCH) slot, and transmitting the at least one codebook entry to the network entity via at least one PUCCH transmission.

公开(公告)号：US12184307B2

公开(公告)日：2024-12-31

申请号：US17646378

申请日：2021-12-29

Applicant: Western Digital Technologies, Inc.

Inventor： Shay Benisty ,  Judah Gamliel Hahn ,  Ariel Navon

IPC: H03M13/45

Abstract: The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

公开(公告)号：US12183386B2

公开(公告)日：2024-12-31

申请号：US17903750

申请日：2022-09-06

Applicant: Western Digital Technologies, Inc.

Inventor： Alexander Bazarsky ,  Judah Gamliel Hahn ,  Michael Ionin

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/56

Abstract: The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.

公开(公告)号：US12183367B2

公开(公告)日：2024-12-31

申请号：US18436581

申请日：2024-02-08

Applicant: Western Digital Technologies, Inc.

Inventor： Junzo Noda ,  Robert G. Biskeborn

IPC: G11B21/10

Abstract: The present disclosure generally relates to a tape drive. The tape drive comprises a first tape head and a second tape head linearly aligned with one another, where the first tape head and the second tape head are configured to concurrently operate. The first tape head and the second tape head each comprise a plurality of write transducers, a plurality of read transducers, and a plurality of servo transducers. The tape drive further comprises a first actuator coupled to the first tape head and a second actuator coupled to the second tape head. The first and second actuators are configured to independently tilt and move the first and second tape heads, respectively. Tilting and moving the first and second tape heads individually enables the tape drive to compensate for non-linear tape dimensional stability effects.