THERMAL BREAK BETWEEN A SUBSTRATE PROCESSING CHAMBER AND SUBSTRATE HANDLING CHAMBER

    公开(公告)号:US20240426381A1

    公开(公告)日:2024-12-26

    申请号:US18745241

    申请日:2024-06-17

    Abstract: Thermal breaks and/or gaps between portions of interfacing surfaces of two chambers reduce heat transfer between the chambers. An interface surface (e.g., of a gate valve) includes (i) a base surface; (ii) a raised ring surface extending outward beyond the base surface, wherein the raised ring surface extends around a gate valve access opening; (iii) a seal support surface extending around the raised ring surface; and (iv) at least one raised boss surface extending outward beyond the base surface. The interface surface defines an outer perimeter having a total interface area. The raised ring surface and raised boss surface(s) define at least a portion of a total contacting surface area of the interface surface that is spaced outward from the base surface. The total contacting surface area of the interface surface is less than 10% of the total interface area and/or less than 10% of the base surface's surface area.

    METHOD OF FORMING A LAYER BY ALD
    33.
    发明申请

    公开(公告)号:US20240425984A1

    公开(公告)日:2024-12-26

    申请号:US18748983

    申请日:2024-06-20

    Abstract: A method of forming a layer of a material on one or more substrates by ALD is disclosed. Embodiments of the presently described method comprise performing a plurality of deposition cycles comprising at least two precursors pulses with intervening purge pulses to form the layer of the material on the one or more substrates. During each deposition cycle, a ratio of the process chamber pressure during each precursor pulse of the at least two precursor pulses to the process chamber pressure during an intervening purge pulse is equal or different from one another.

    WAFER HANDLING ASSEMBLY
    38.
    发明申请

    公开(公告)号:US20240395586A1

    公开(公告)日:2024-11-28

    申请号:US18672416

    申请日:2024-05-23

    Inventor: Adriaan Garssen

    Abstract: A wafer handling assembly, a semiconductor processing apparatus comprising the wafer handling assembly and a method of forming a layer on a plurality of wafers is disclosed. Embodiments of the described wafer handling assembly comprise a boat having three boat supports per wafer for supporting the wafer in the boat and an end effector comprising three end effector supports for supporting a wafer on the end effector.

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