公开(公告)号：US08248883B1

公开(公告)日：2012-08-21

申请号：US12873041

申请日：2010-08-31

Applicant: Ting Lu ,  Kam-Wing Li ,  Anatoly Belkin ,  Ahmad R. Ansari

Inventor： Ting Lu ,  Kam-Wing Li ,  Anatoly Belkin ,  Ahmad R. Ansari

IPC: G11C8/00

CPC classification number: G11C8/06 ,  G06F2213/0038

Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

Abstract translation: 用于实现基于非易失性输入/输出（I / O）设备的存储器的系统可以包括被配置为接收指定数据单元的处理器请求的接口。 数据单元可以由处理器地址指定。 该系统可以包括耦合到接口的地址数据转换器。 地址数据转换器可以被配置为将数据单元的处理器地址与非易失性I / O设备内的数据块相关联。 该系统还可以包括耦合到地址数据转换器的I / O控制器。 I / O控制器可配置为向非易失性I / O设备发出指定数据块的非易失性I / O设备命令。

公开(公告)号：US08185720B1

公开(公告)日：2012-05-22

申请号：US12043097

申请日：2008-03-05

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

IPC: G06F15/76

CPC classification number: G06F15/7889

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.

Abstract translation: 硬连线核心嵌入具有可编程电路的集成电路中。 硬接线芯具有微处理器; 耦合到微处理器的处理器本地总线的交叉开关互连; 以及耦合到交叉开关互连的存储器控​​制器接口。 交叉连接提供用于将硬连线核心耦合到可编程电路的管线。 微处理器，交叉开关互连和存储器控制器接口都能够以第一操作频率操作，并且存储器控制器接口还能够被设置为在第二操作频率下操作，其具有相对于 第一个操作频率。 交叉开关互连被配置为将由微处理器发起的事务定向到存储器控制器接口，用于经由存储器控制器访问耦合到存储器控制器接口的一个或多个存储器件。 附加或其他接口可以耦合到交叉开关互连。

公开(公告)号：US07865698B1

公开(公告)日：2011-01-04

申请号：US12057356

申请日：2008-03-27

Applicant: Kathryn S. Purcell ,  Ahmad R. Ansari

Inventor： Kathryn S. Purcell ,  Ahmad R. Ansari

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30185 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-code that is not masked to determine whether the op-code is for a slave device. The decoding of the second portion is performed by a controller having a decoder, and the controller bridges the master device for communication with the slave device. The decoding of the first portion of the bits is performed by the slave device. The first portion of the bits identifies an instruction from a group of instructions, and the group of instructions uses a single configuration register of registers of the controller.

Abstract translation: 一种用于解码的方法，包括：从主设备获得操作码; 设置模式来掩蔽操作码的比特的第一部分，其中比特的第一部分被视为通配符值; 以及对未被屏蔽的操作代码的第二部分进行解码以确定操作码是否用于从设备。 第二部分的解码由具有解码器的控制器执行，并且控制器桥接主设备以与从设备进行通信。 比特的第一部分的解码由从设备执行。 位的第一部分识别来自一组指令的指令，并且该组指令使用控制器的寄存器的单个配置寄存器。

公开(公告)号：US07539848B1

公开(公告)日：2009-05-26

申请号：US11242177

申请日：2005-09-30

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F15/16

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.

Abstract translation: 公开了一种包括集成电路装置中的逻辑电路的系统，其中所述逻辑电路包括包括多个可配置逻辑块，切换块和输入/输出块的逻辑结构，其中所述逻辑结构根据配置数据 从外部存储器提供给所述集成电路装置，并且所述逻辑结构的至少一部分被配置为配置的处理器，以根据所述配置数据执行第一固定逻辑功能。 固定逻辑处理器，第一辅助处理接口，第二固定逻辑处理器，第二辅助处理接口，能够与配置的处理器进行通信，其中所配置的处理器保持配置以使固定逻辑处理器和第二固定逻辑处理器能够访问 配置的处理器执行固定逻辑功能。

公开(公告)号：US07313794B1

公开(公告)日：2007-12-25

申请号：US10354813

申请日：2003-01-30

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F9/46 ,  G06F13/00

CPC classification number: G06F13/1663 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/52

Abstract: Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.

Abstract translation: 描述用于同步对多个处理器之间共享的存储器的访问的方法和装置。 在一个示例中，多个处理器中的每一个包括用于与存储器通信的主总线和辅助总线。 同步块耦合到多个处理器中的每一个的辅助总线。 同步块包括至少一个信号量，用于控制多个处理器之间存储在存储器内的至少一个数据段的访问。

公开(公告)号：US06813701B1

公开(公告)日：2004-11-02

申请号：US09375328

申请日：1999-08-17

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F9312

CPC classification number: G06F9/383 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3455

Abstract: A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. A vector is partitioned by the compiler into variable-sized streams which are transferred into and out of the processor as burst transactions. The compiler schedules transfers of vector streams required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers and each vector buffer is used at a specific time. The compiler partitions a vector buffer into the variable-sized streams depending on the number of vectors buffers required by an application program and the size required for each stream. Each vector buffer is allocated for exclusive use by an application program that is executing in the data processor. A synchronization instruction is used to allow all VTU instructions issued prior to the synchronization instruction to finish before any VTU instructions issued after the synchronization instruction may begin. Instructions for controlling access to the vector buffer pool are also included.

Abstract translation: 用于向量传送单元中用于处理计算机系统中的存储器和数据处理器之间的向量数据传送的编译器和向量数据传输指令。 编译器识别应用程序中矢量数据的使用，并实现一个或多个矢量指令，用于在用于对矢量数据执行计算的存储器和寄存器之间传送矢量数据。 向量被编译器划分为可变大小的流，这些流作为突发事务被传入和传出处理器。 编译器调度计算中所需的向量流的传输，使得在矢量数据的后续部分被传送时执行向量数据的一部分上的计算。 向量缓冲池被划分为一个或多个向量缓冲区，并且在特定时间使用每个向量缓冲区。 编译器根据应用程序所需的向量缓冲区数量和每个流所需的大小，将向量缓冲区分成可变大小的流。 每个向量缓冲区被分配给正在数据处理器中执行的应用程序专用。 同步指令用于允许同步指令之前发出的所有VTU指令在同步指令开始之后发出的任何VTU指令之前完成。 还包括控制向量缓冲池访问的指令。

公开(公告)号：US06742106B2

公开(公告)日：2004-05-25

申请号：US10352511

申请日：2003-01-28

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F9312

CPC classification number: G06F9/30043 ,  G06F9/30087 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3861

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting. An address error exception occurs when the ending address of the vector data to be transferred is not within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined in parallel with determining the starting address of the vector data to be transferred.

公开(公告)号：US06625720B1

公开(公告)日：2003-09-23

申请号：US09375718

申请日：1999-08-17

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F1576

CPC classification number: G06F15/8084 ,  G06F9/3836 ,  G06F9/3857

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector instructions are used for transferring the vector data between memory and registers used to perform calculations on the vector data. The transfers of portions of the vector data required in a calculation are scheduled so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers based on configuration information including the number of vectors buffers required by an application program and the size required for each vector buffer. The vector buffers are allocated for exclusive use by an application program that is executing in the data processor. Vector data transfer instructions are posted in a vector transfer instruction queue and are executed in the order they are posted to the instruction queue. A synchronization instruction is used to block the execution of vector transfer instructions that are posted in the instruction queue after the synchronization instruction.

Abstract translation: 用于处理计算机系统中的存储器和数据处理器之间的矢量数据传送的矢量传送单元。 矢量指令用于在用于对矢量数据执行计算的存储器和寄存器之间传送矢量数据。 调度计算中所需的向量数据的部分的传送，以便在矢量数据的后续部分被传送的同时对矢量数据的一部分进行计算。 基于包括应用程序所需的向量缓冲器的数量和每个向量缓冲器所需的大小的配置信息将向量缓冲池划分成一个或多个向量缓冲器。 向量缓冲区被分配给正在数据处理器中执行的应用程序专用。 向量数据传输指令被张贴在向量传送指令队列中，并按照它们被发布到指令队列的顺序被执行。 同步指令用于阻止在同步指令之后在指令队列中发布的向量传送指令的执行。