公开(公告)号：US06886092B1

公开(公告)日：2005-04-26

申请号：US10001871

申请日：2001-11-19

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 当可编程门阵列中嵌入的固定逻辑处理器检测到定制操作代码时，开始用于处理可编程门阵列内的数据的方法和装置。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，该处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。

公开(公告)号：US07269805B1

公开(公告)日：2007-09-11

申请号：US10836995

申请日：2004-04-30

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。

公开(公告)号：US07194600B2

公开(公告)日：2007-03-20

申请号：US11059748

申请日：2005-02-17

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/44

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 用于在可编程门阵列内处理数据的方法和装置包括嵌入可编程门阵列内并检测定制操作码的第一固定逻辑处理器和第二固定逻辑处理器。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。

公开(公告)号：US06693452B1

公开(公告)日：2004-02-17

申请号：US10082883

申请日：2002-02-25

Applicant: Ahmad R. Ansari ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Stephen M. Douglass

IPC: H03K19177

CPC classification number: H03K19/1776 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interconnecting logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuitry and programmable logic circuitry. The various designs are geared towards many goals including allowing fail-safe operation, facilitating the ease of interface between fixed logic circuitry and programmable logic fabric, among other issues.

Abstract translation: 互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。 互连逻辑包括互连瓦片，并且还可以包括互连逻辑。 互连瓦片提供固定逻辑电路的输入和/或输出与可编程逻辑结构的互连之间的选择性连接。 当互连逻辑包含时，提供了逻辑电路，用于调节固定逻辑电路和可编程逻辑结构之间的数据传输。 本发明针对具有固定逻辑电路和可编程逻辑电路的设备的布局和楼层规划的各种需求和要求。 各种设计旨在实现许多目标，包括允许故障安全操作，便于固定逻辑电路和可编程逻辑架构之间的接口以及其他问题。

公开(公告)号：US07406670B1

公开(公告)日：2008-07-29

申请号：US11888774

申请日：2007-08-01

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45 ,  H03K19/00

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。

公开(公告)号：US07231621B1

公开(公告)日：2007-06-12

申请号：US10837395

申请日：2004-04-30

Applicant: Nigel G. Herron ,  Ahmad R. Ansari ,  Stephen M. Douglass ,  Anthony Correale, Jr. ,  Leslie M. DeBruyne

Inventor： Nigel G. Herron ,  Ahmad R. Ansari ,  Stephen M. Douglass ,  Anthony Correale, Jr. ,  Leslie M. DeBruyne

IPC: G06F9/45 ,  G01R31/28

CPC classification number: G01R31/31718 ,  G01R31/31725 ,  G01R31/318519

Abstract: Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.

Abstract translation: 用于生成具有嵌入式处理器的可编程逻辑器件的测试程序的方法和装置。 获得预定代码以锻炼所识别的至少一个速度限制路径。 对于预定代码，添加包装器代码以提供测试程序，包装器代码部分地用于将预定代码加载到嵌入式处理器的高速缓存中，用于测试所识别的嵌入式处理器的至少一个速度限制路径。

公开(公告)号：US06522167B1

公开(公告)日：2003-02-18

申请号：US09757760

申请日：2001-01-09

Applicant: Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

Inventor： Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

IPC: G06F738

CPC classification number: G06F15/7867

Abstract: A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Abstract translation: 具有用户可配置存储器控制器，一个或多个块RAMS和处理器核的数据处理系统可以被配置在单个现场可编程门阵列（FPGA）中。 块RAM的地址深度和等待状态的数量可以由用户选择，并且可以在FPGA的配置之前设置，也可以使用处理器核心的指令进行编程。 还公开了可以优化地址深度和等待状态数以达到性能水平的算法。 本发明可以应用于具有单独的指令和数据侧的设计。

公开(公告)号：US07539848B1

公开(公告)日：2009-05-26

申请号：US11242177

申请日：2005-09-30

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F15/16

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.

Abstract translation: 公开了一种包括集成电路装置中的逻辑电路的系统，其中所述逻辑电路包括包括多个可配置逻辑块，切换块和输入/输出块的逻辑结构，其中所述逻辑结构根据配置数据 从外部存储器提供给所述集成电路装置，并且所述逻辑结构的至少一部分被配置为配置的处理器，以根据所述配置数据执行第一固定逻辑功能。 固定逻辑处理器，第一辅助处理接口，第二固定逻辑处理器，第二辅助处理接口，能够与配置的处理器进行通信，其中所配置的处理器保持配置以使固定逻辑处理器和第二固定逻辑处理器能够访问 配置的处理器执行固定逻辑功能。

公开(公告)号：US08006021B1

公开(公告)日：2011-08-23

申请号：US12057326

申请日：2008-03-27

Applicant: Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

Inventor： Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract translation: 描述了一种用于嵌入IC的处理器块ASIC核心的处理器局部总线桥。 核心逻辑到核心逻辑桥包括从处理器本地总线接口，耦合到从属处理器本地总线接口的交叉开关和耦合到交叉开关的主处理器本地总线接口。 从处理器本地总线接口和主处理器本地总线接口通过交叉开关彼此耦合，用于核心逻辑的第一和第二部分之间的双向通信。 桥接器提供用于桥接的速率适配，以使用与交叉开关相关联的操作频率，其具有比与主处理器和从属处理器局部总线接口的核心逻辑侧相关联的操作频率更大的操作频率。

公开(公告)号：US07737725B1

公开(公告)日：2010-06-15

申请号：US12098400

申请日：2008-04-04

Applicant: Ahmad R. Ansari ,  Kam-Wing Li

Inventor： Ahmad R. Ansari ,  Kam-Wing Li

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F15/7867

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract translation: 描述了用于处理器块的设备控制寄存器控制器专用集成电路（“ASIC”）核心。 器件控制寄存器从器件块耦合到器件控制寄存器控制器，并且可以访问处理器块ASIC核心的多个接口的器件寄存器。 主设备接口用于将处理器块ASIC核心外部的至少一个从设备耦合到设备控制寄存器控制器。 从设备接口用于将处理器块ASIC核心外部的主设备耦合到设备控制寄存器控制器。