公开(公告)号：US20130018272A1

公开(公告)日：2013-01-17

申请号：US13638466

申请日：2011-03-07

申请人： Atsushi Hori

发明人： Atsushi Hori

IPC分类号： A61B5/024

CPC分类号： A61B5/0285 ,  A61B5/021 ,  A61B5/02125 ,  A61B5/02225 ,  A61B5/0295 ,  A61B5/7203 ,  A61B5/7239 ,  A61B2560/0261

摘要： A pulse wave velocity measurement device comprises a pulse wave detection unit (110) for detecting a pulse wave in a living body, a pulse wave velocity calculation unit (120) for calculating a pulse wave velocity on basis of the pulse wave detected by the pulse wave detection unit (110), and a pulse wave velocity correction unit (130) for correcting the pulse wave velocity calculated by the pulse wave velocity calculation unit (120) so as to eliminate an increment in the pulse wave velocity that results from influence of hydrostatic pressures caused according to a position of the living body. Thus, the pulse wave velocity measurement device can be provided that are capable of accurate measurement of the pulse wave velocity without being influenced by the hydrostatic pressures caused according to the position of the living body.

摘要翻译： 脉搏波速度测量装置包括用于检测生物体中的脉搏波的脉搏波检测单元（110），用于根据由脉冲检测到的脉搏波计算脉搏波速度的脉搏波速度计算单元（120） 波形检测单元（110）和用于校正由脉搏波速度计算单元（120）计算出的脉搏波速度的脉搏波速度校正单元（130），以消除由脉冲波速度计算单元 根据生物体的位置引起的静水压力。 因此，可以提供脉搏波速度测量装置，其能够精确地测量脉搏波速度，而不受根据生物体的位置引起的静水压力的影响。

公开(公告)号：US20100277652A1

公开(公告)日：2010-11-04

申请号：US12768524

申请日：2010-04-27

申请人： Atsushi Hori ,  Koji Yamazaki ,  Kinya Kamiguchi

发明人： Atsushi Hori ,  Koji Yamazaki ,  Kinya Kamiguchi

IPC分类号： H04N5/66 ,  H01J1/54 ,  G09G5/00 ,  H01J9/00

CPC分类号： H01J29/92 ,  H01J29/925 ,  H01J31/127 ,  H01J2329/92 ,  H04N5/66

摘要： In a display panel, a conductive member subjected to a prescribed electric potential lower than an anode potential is disposed on a first insulating substrate at a location spaced apart from an anode terminal subjected to the anode potential. An insulating member is disposed on the conductive member such that the insulating member includes a part located closer to the anode terminal than an end, on a side facing the anode terminal, of the conductive member and such that a gap is provided between the part and the first insulating substrate.

摘要翻译： 在显示面板中，经受比阳极电位低的规定电位的导电构件设置在与经受阳极电位的阳极端子间隔开的位置处的第一绝缘基板上。 绝缘构件设置在导电构件上，使得绝缘构件包括比导电构件的面向阳极端子的一侧的端部更靠近阳极端子的部分，并且在该部分和 第一绝缘基板。

公开(公告)号：US5409847A

公开(公告)日：1995-04-25

申请号：US141727

申请日：1993-10-27

申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823814 ,  Y10S148/147

摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

公开(公告)号：USD669328S1

公开(公告)日：2012-10-23

申请号：US29410346

申请日：2012-01-06

申请人： Tomonori Kawase ,  Kenji Abe ,  Syo Kume ,  Atsushi Hori

设计人： Tomonori Kawase ,  Kenji Abe ,  Syo Kume ,  Atsushi Hori

公开(公告)号：USD669327S1

公开(公告)日：2012-10-23

申请号：US29410333

申请日：2012-01-06

申请人： Tomonori Kawase ,  Kenji Abe ,  Syo Kume ,  Atsushi Hori

设计人： Tomonori Kawase ,  Kenji Abe ,  Syo Kume ,  Atsushi Hori

公开(公告)号：US20120226174A1

公开(公告)日：2012-09-06

申请号：US13508933

申请日：2010-11-01

申请人： Yutaka Ikeda ,  Atsushi Hori

发明人： Yutaka Ikeda ,  Atsushi Hori

IPC分类号： A61B5/024

CPC分类号： A61B5/0285 ,  A61B5/02007 ,  A61B5/021 ,  A61B5/02125 ,  A61B5/7239

摘要： In a pulse wave velocity measurement device (10), reference times (T1, T2) for an ejection wave component (S1) and a reflected component (S2) of a pulse wave S are detected by a reference time detection unit (2), and amplitudes (W1, W2) of the pulse wave (S) that correspond to the reference times (T1, T2) for the ejection wave component (S1) and the reflected wave component (S2) are detected by a pulse wave amplitude detection unit (3). A pulse wave velocity detection unit (5) finds a velocity (PWV1) of the pulse wave (S) on basis of the reference times (T1, T2) for the ejection wave component (S1) and the reflected wave component (S2) and the amplitudes (W1, W2) of the pulse wave (S) that correspond to the reference times (T1, T2) for the ejection wave component (S1) and the reflected wave component (S2). Thus the pulse wave velocity can be measured with high accuracy in consideration of a difference between the pulse wave velocities of the ejection wave and the reflected wave which difference is caused by a difference between the amplitude of the ejection wave component (S1) and the amplitude of the reflected wave component (S2).

摘要翻译： 在脉搏波速度测量装置（10）中，由基准时间检测部（2）检测喷射波分量（S1）的基准时间（T1，T2）和脉波S的反射分量（S2） 并且通过脉波振幅检测单元检测与喷射波分量（S1）和反射波分量（S2）的基准时间（T1，T2）对应的脉搏波（S）的振幅（W1，W2） （3）。 脉搏波速度检测单元（5）根据喷射波分量（S1）和反射波分量（S2）的基准时间（T1，T2）和反射波分量（S2），求出脉搏波（S）的速度（PWV1） 对应于喷射波分量（S1）的参考时间（T1，T2）和反射波分量（S2）的脉冲波（S）的振幅（W1，W2）。 因此，考虑到喷射波的脉冲波速度与反射波之间的差异，可以以高精度测量脉搏波速度，该差异是由喷射波分量（S1）的幅度与振幅之间的差引起的 的反射波分量（S2）。

公开(公告)号：US07728501B2

公开(公告)日：2010-06-01

申请号：US11623523

申请日：2007-01-16

申请人： Atsushi Hori

发明人： Atsushi Hori

IPC分类号： H01J1/62

CPC分类号： H01J29/028 ,  H01J29/467 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/4604 ,  H01J2329/863 ,  H01J2329/8635 ,  H01J2329/8645 ,  H01J2329/865

摘要： An image display apparatus includes an envelope, first to third electroconductive members disposed in the envelope, a plate-like spacer disposed between the first and third members and between the second and third members, and a circuit for supplying a potential to the first member and supplying a potential lower than that of the first member to the second and third members. When a sheet resistance between a first region of the spacer to which the potential is supplied from the first member and a second region of the spacer to which the potential is supplied from the second member is defined as ρf [Ω/□] and a sheet resistance between a third region of the spacer to which the potential is supplied from the third member and a region located between the first and second regions is defined as ρr [Ω/□], a condition 1/100

摘要翻译： 图像显示装置包括外壳，设置在外壳中的第一至第三导电构件，设置在第一和第三构件之间以及第二和第三构件之间的板状间隔件，以及用于向第一构件供应电位的电路， 向第二和第三成员提供比第一成员低的电位。 当从第一构件供给电位的间隔物的第一区域和从第二构件供给电位的间隔物的第二区域之间的薄层电阻被定义为＆rgr; f [＆OHgr; /□] 并且从第三构件提供电位的间隔物的第三区域和位于第一和第二区域之间的区域之间的薄层电阻被定义为＆rgr; r [＆OHgr; /□]，条件1/100 < ＆rgr; r /＆rgr; f＆nlE; 40满足。

公开(公告)号：US06770517B2

公开(公告)日：2004-08-03

申请号：US10028803

申请日：2001-12-28

申请人： Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

发明人： Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  Y10S438/91

摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

摘要翻译： 在形成在绝缘体层上的硅层中，形成与沟道区域和源极/漏极区域相邻的晶格缺陷区域，沟道区域的下部部分作为高浓度沟道区域。 通过在晶格缺陷区域中的复合消除在沟道区域中产生的空穴 - 电子对的空穴，从而抑制由于空穴的积累而产生的双极性运算并增加源极/漏极击穿电压。 寄生晶体管的阈值由高浓度沟道区域增加，以便在OFF状态下减少漏电流。 或者，可以通过提供构成并在沟道和源极区域之间作为pn二极管工作的高浓度扩散层而不是晶格缺陷区域，而将孔移动到源极区域以消失。 因此，可以提供一种SOI晶体管，其不会由于衬底浮置效应而导致的源极/漏极击穿电压降低，并且由于寄生晶体管的激活而导致小的漏电流。

公开(公告)号：US06380585B1

公开(公告)日：2002-04-30

申请号：US09588308

申请日：2000-06-06

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US06358799B2

公开(公告)日：2002-03-19

申请号：US09727536

申请日：2000-12-04

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。