公开(公告)号：US20090031087A1

公开(公告)日：2009-01-29

申请号：US11828811

申请日：2007-07-26

申请人： Blaine D. Gaither ,  Benjamin D. Osecky ,  Gerald J. Kaufman, JR.

发明人： Blaine D. Gaither ,  Benjamin D. Osecky ,  Gerald J. Kaufman, JR.

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0842 ,  G06F2212/1048

摘要： A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.

摘要翻译： 系统包括多个高速缓存代理，耦合到高速缓存代理的计算实体以及计算实体可访问的可编程掩码。 对于至少一个存储器地址，可编程掩码指示可以接收与存储器地址相关联的窥探请求的那些缓存代理。 基于掩码，计算实体将与存储器地址相关联的窥探请求发送到只能由掩码识别的缓存代理作为可以接收与存储器地址相关联的窥探请求的缓存代理。

公开(公告)号：US20080222343A1

公开(公告)日：2008-09-11

申请号：US11683573

申请日：2007-03-08

申请人： Judson E. Veazey ,  Blaine D. Gaither

发明人： Judson E. Veazey ,  Blaine D. Gaither

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.

摘要翻译： 提供了一种用于将数据预取入高速缓冲存储器的方法。 存储来自至少一个处理器的多个数据请求中的每一个的第一高速缓存行地址。 将来自处理器的下一个数据请求的第二高速缓存行地址与第一高速缓存行地址进行比较。 如果第二高速缓存行地址与第一高速缓存线地址之一相邻，则与第二高速缓存行地址相邻的与第三高速缓存行地址相关联的数据被预取到高速缓冲存储器中，如果尚未存在 缓存内存。

公开(公告)号：US20080133834A1

公开(公告)日：2008-06-05

申请号：US11635316

申请日：2006-12-05

申请人： Blaine D. Gaither ,  Verna Knapp

发明人： Blaine D. Gaither ,  Verna Knapp

IPC分类号： G06F12/08

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.

摘要翻译： 一种用于处理在串行结构上的存储请求的方法，包括将用于串行结构上的通信的地址格式化为多个字段，所述多个字段包括包括至少一个集合选择位的字段和包括至少一个标签位的字段。 该地址在串行结构上传送，其中该字段包括首先通信的至少一个选择位。

公开(公告)号：US07096320B2

公开(公告)日：2006-08-22

申请号：US10004195

申请日：2001-10-31

申请人： Blaine D. Gaither ,  Benjamin D. Osecky

发明人： Blaine D. Gaither ,  Benjamin D. Osecky

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/122

摘要： A cache memory system can determine that an entry is stale if the entry has not been accessed or modified for a predetermined time. If an entry is stale, the entry may be preemptively evicted. The predetermined time is made dynamically variable. A computer system can adjust the time to optimize a measure of performance. In a specific example, evicted lines are temporarily stored in an eviction queue. The time is adjusted to be as short as possible without substantially increasing the number of lines that must be recalled from the eviction queue.

公开(公告)号：US06810465B2

公开(公告)日：2004-10-26

申请号：US10004193

申请日：2001-10-31

申请人： Blaine D. Gaither ,  Benjamin D. Osecky

发明人： Blaine D. Gaither ,  Benjamin D. Osecky

IPC分类号： G06F1200

CPC分类号： G06F12/0811 ,  G06F12/0833 ,  G06F12/122 ,  G06F12/126 ,  Y10S707/99932

摘要： A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may further improve performance by limiting the number of dirty entries in the cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-ache transfer when the number exceeds a predetermined threshold.

摘要翻译： 缓存系统通过限制高速缓存中脏条目的数量来提高性能。 高速缓存系统可以通过限制高速缓存中可能受到高速缓存到高速缓存传输的脏条目的数量来进一步提高性能。 在第一示例中，高速缓存系统对高速缓存中的脏条目的总数进行计数，并且当计数超过预定阈值时，预先将至少一个脏条目排除。 在一个变型中，高速缓存系统计算由高速缓存到高速缓存传输产生的脏高速缓存条目，并且当数量超过预定阈值时，将至少一个由高速缓存到交换传输产生的脏条目排斥。

公开(公告)号：US06434672B1

公开(公告)日：2002-08-13

申请号：US09515727

申请日：2000-02-29

申请人： Blaine D. Gaither

发明人： Blaine D. Gaither

IPC分类号： G06F1212

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/084

摘要： A computer system comprising a plurality of processors each having dedicated cache memories, another level of cache shared by the plurality of caches, and a main memory. The processors and the shared cache act as peers on a bus located between the processors and main memory. All data placed upon the bus by the main memory as a result of a read transaction are written into the shared cache. The shared cache does not initiate any transactions.

摘要翻译： 一种包括多个处理器的计算机系统，每个处理器具有专用高速缓冲存储器，由多个高速缓冲存储器共享的另一级别的高速缓存和主存储器。 处理器和共享缓存在位于处理器和主存储器之间的总线上作为对等体。 作为读取事务的结果，由主存储器放置在总线上的所有数据被写入共享高速缓存。 共享缓存不会启动任何事务。

公开(公告)号：US06405322B1

公开(公告)日：2002-06-11

申请号：US09290942

申请日：1999-04-13

申请人： Blaine D. Gaither ,  John A. Morrison ,  John R. Feehrer

发明人： Blaine D. Gaither ,  John A. Morrison ,  John R. Feehrer

IPC分类号： G06F1216

CPC分类号： G06F12/0831 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/0796

摘要： A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid. If the state of the cached line is valid and consistent, such as the “Modified uncached” (Mu) state in a MuMESI protocol, then the line may be written to main memory or provided to a snoop requester.

摘要翻译： 描述用于从地址错误中恢复的设备和方法。 当在本地信道（例如本地总线）上检测到地址错误时，读取与本地信道相关联的一行或多行高速缓冲存储器的一致性状态，并作出响应。 相关性状态的读取范围从所有高速缓存行的完整和主动询问，到选择性和被动询问，例如响应窥探请求。 如果数据状态一致性未知，例如当MESI状态为M（M）或Exclusive（E）时，则主存储器中的相应数据中毒。 中毒可以通过在主存储器中写入可检测但不可恢复的错误模式来实现。 或者，通过在系统总线上发出硬错误来实现相同的效果。 如果询问的高速缓存行的数据状态一致性为Shared（S）或Invalid（I），则该行可能会被忽略或标记为无效的行。 如果缓存行的状态是有效且一致的，例如MuMESI协议中的“Modified uncached”（Mu）状态，则该行可以写入主存储器或提供给窥探请求者。

公开(公告)号：US08688890B2

公开(公告)日：2014-04-01

申请号：US11635316

申请日：2006-12-05

申请人： Blaine D. Gaither ,  Verna Knapp

发明人： Blaine D. Gaither ,  Verna Knapp

IPC分类号： G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.

摘要翻译： 一种用于处理在串行结构上的存储请求的方法，包括将用于串行结构上的通信的地址格式化为多个字段，所述多个字段包括包括至少一个集合选择位的字段和包括至少一个标签位的字段。 该地址在串行结构上传送，其中该字段包括首先通信的至少一个选择位。

公开(公告)号：US08683139B2

公开(公告)日：2014-03-25

申请号：US11554827

申请日：2006-10-31

申请人： Blaine D. Gaither ,  Patrick Knebel

发明人： Blaine D. Gaither ,  Patrick Knebel

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897

摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。

公开(公告)号：US20130232124A1

公开(公告)日：2013-09-05

申请号：US13412146

申请日：2012-03-05

申请人： Blaine D. GAITHER

发明人： Blaine D. GAITHER

IPC分类号： G06F7/00

CPC分类号： G06F16/1748

摘要： A storage node receives a file. The storage node determines whether the file is stored on the storage node by comparing a hash value computed for content of the received file to hash values for content stored on the storage node. The storage node transfers a name and address of the file to a directory node.

摘要翻译： 存储节点接收文件。 存储节点通过将为接收到的文件的内容计算的散列值与存储在存储节点上的内容的哈希值进行比较来确定该文件是否存储在存储节点上。 存储节点将文件的名称和地址传送到目录节点。