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公开(公告)号：US20090031087A1
公开(公告)日：2009-01-29
申请号：US11828811
申请日：2007-07-26
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0842 , G06F2212/1048
摘要： A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.
摘要翻译： 系统包括多个高速缓存代理，耦合到高速缓存代理的计算实体以及计算实体可访问的可编程掩码。 对于至少一个存储器地址，可编程掩码指示可以接收与存储器地址相关联的窥探请求的那些缓存代理。 基于掩码，计算实体将与存储器地址相关联的窥探请求发送到只能由掩码识别的缓存代理作为可以接收与存储器地址相关联的窥探请求的缓存代理。
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公开(公告)号：US07765363B2
公开(公告)日：2010-07-27
申请号：US11828811
申请日：2007-07-26
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0842 , G06F2212/1048
摘要： A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.
摘要翻译： 系统包括多个高速缓存代理，耦合到高速缓存代理的计算实体以及计算实体可访问的可编程掩码。 对于至少一个存储器地址，可编程掩码表示可以接收与存储器地址相关联的窥探请求的那些缓存代理。 基于掩码，计算实体将与存储器地址相关联的窥探请求发送到只能由掩码识别的缓存代理作为可以接收与存储器地址相关联的窥探请求的缓存代理。
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3.发明授权Computer performance improvement by adjusting a count used for preemptive eviction of cache entries 失效通过调整用于抢先驱逐缓存条目的计数来提高计算机性能公开(公告)号：US06813691B2
公开(公告)日：2004-11-02
申请号：US10001584
申请日：2001-10-31
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0831 , G06F12/0897 , Y10S707/99932
摘要： A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.
摘要翻译： 缓存系统通过限制高速缓存中脏条目的数量来提高性能。 缓存系统可以通过限制高速缓存中可能受到高速缓存到高速缓存传输的脏条目的数量来进一步提高性能。 在第一示例中，高速缓存系统对高速缓存中的脏条目的总数进行计数，并且当计数超过预定阈值时，预先将至少一个脏条目排除。 在一个变型中，缓存系统计算由高速缓存到高速缓存传输所产生的脏缓存条目，并且当数量超过预定阈值时，将至少一个由高速缓存到高速缓存传输产生的脏条目驱逐出去。 对于任一系统，可以动态地改变预定阈值以确定优化性能的值。
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公开(公告)号：US20080016288A1
公开(公告)日：2008-01-17
申请号：US11485409
申请日：2006-07-12
IPC分类号： G06F13/00
CPC分类号： G06F12/0842 , G06F12/0864 , G06F12/1408
摘要： Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.
摘要翻译： 提供了一种用于唯一地掩蔽每个用户对高速缓冲存储器的寻址的方法，从而降低一个用户对另一用户的定时攻击的风险。 该方法包括向第一用户分配第一掩码值，向第二用户分配第二掩码值。 掩码值彼此独特。 当代表第一用户执行第一指令时，该方法包括应用第一掩码值以设置由第一指令访问的存储器地址中的选择位。 当代表第二用户执行第二指令时，该方法包括应用第二掩码值以设置由第二指令访问的存储器地址中的选择位。 该结果提供了用户之间的额外级别的安全性，并减少了针对相同内存地址的线程或进程的发生。
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公开(公告)号：US20150074316A1
公开(公告)日：2015-03-12
申请号：US14389910
申请日：2012-04-30
申请人： Blaine D. Gaither , Robert J. Brooks , Benjamin D. Osecky , Kathryn A. Evertson , Andrew R. Wheeler , David Fisk
发明人： Blaine D. Gaither , Robert J. Brooks , Benjamin D. Osecky , Kathryn A. Evertson , Andrew R. Wheeler , David Fisk
CPC分类号： G06F13/4027 , G06F11/1666 , G06F12/0284 , G06F13/16 , G06F13/1652 , G06F13/404 , G06F17/30368
摘要： In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.
摘要翻译： 在至少一些示例中，计算节点包括耦合到处理器的处理器和本地存储器。 计算节点还包括耦合到处理器的反射存储器桥。 反射存储器桥映射到分配给至少一个外部计算节点的本地存储器的进入区域，并映射到分配给至少一个外部计算节点的本地存储器的输出区域。
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6.发明授权公开(公告)号：US07096320B2
公开(公告)日：2006-08-22
申请号：US10004195
申请日：2001-10-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/122
摘要： A cache memory system can determine that an entry is stale if the entry has not been accessed or modified for a predetermined time. If an entry is stale, the entry may be preemptively evicted. The predetermined time is made dynamically variable. A computer system can adjust the time to optimize a measure of performance. In a specific example, evicted lines are temporarily stored in an eviction queue. The time is adjusted to be as short as possible without substantially increasing the number of lines that must be recalled from the eviction queue.
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公开(公告)号：US06810465B2
公开(公告)日：2004-10-26
申请号：US10004193
申请日：2001-10-31
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0833 , G06F12/122 , G06F12/126 , Y10S707/99932
摘要： A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may further improve performance by limiting the number of dirty entries in the cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-ache transfer when the number exceeds a predetermined threshold.
摘要翻译： 缓存系统通过限制高速缓存中脏条目的数量来提高性能。 高速缓存系统可以通过限制高速缓存中可能受到高速缓存到高速缓存传输的脏条目的数量来进一步提高性能。 在第一示例中，高速缓存系统对高速缓存中的脏条目的总数进行计数，并且当计数超过预定阈值时，预先将至少一个脏条目排除。 在一个变型中，高速缓存系统计算由高速缓存到高速缓存传输产生的脏高速缓存条目，并且当数量超过预定阈值时，将至少一个由高速缓存到交换传输产生的脏条目排斥。
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公开(公告)号：US20080184194A1
公开(公告)日：2008-07-31
申请号：US11626922
申请日：2007-01-25
IPC分类号： G06F9/44
CPC分类号： G06F9/3851
摘要： A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.
摘要翻译： 公开了一种在计算机系统，计算机系统和相关的编译方法中执行操作的方法。 在一个实施例中，执行方法包括提供具有至少一个线程的编译代码，其中所述至少一个线程中的每一个包括相应的多个块，并且每个相应块包括相应的预取组件和相应的执行组件。 所述方法还包括从所述至少一个线程的第一线程的第一块执行第一预取组件，在执行所述第一预取组件之后执行第一附加组件，以及执行来自所述第一执行组件的第一执行组件 第一个线程的第一个块。 在执行第一附加组件之后执行第一执行组件，并且第一附加组件来自不是第一块的第一个线程的第二个线程或另一个块。
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9.发明授权Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device 有权在检测到处理器冷却装置的损坏之后提供多处理器计算机系统的持续操作的方法和装置公开(公告)号：US06792550B2
公开(公告)日：2004-09-14
申请号：US09775404
申请日：2001-01-31
IPC分类号： G06F100
CPC分类号： G06F11/004 , G06F1/206 , G06F11/006 , G06F11/20 , G06F11/3006 , G06F11/3017 , G06F11/3024 , G06F11/3058 , H05K7/20836 , Y02D10/16
摘要： A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs. After the cooling device has been replaced and is operating normally, the CPU can be powered back up, interrupts can be enabled, and the CPU can once again execute user and operating system processes.
摘要翻译： 在与中央处理单元（CPU）耦合的冷却装置发生故障之后，多处理器计算机系统继续运行。 根据本发明，检测到冷却装置的即将发生的故障，并且将所有用户和操作系统处理从耦合到故障冷却装置的受影响的CPU移动到一个或多个其他CPU。 然后更改系统状态，以便受影响的CPU不再接收和处理中断，并且与受影响的CPU相关联的所有内存缓存都将刷新到主内存，以确保高速缓存一致性。 此时，CPU处于掉电状态或置于低功耗模式，允许CPU在没有冷却设备的情况下运行，而从中止CPU中删除的进程在其他CPU上继续执行。 在冷却装置更换并正常运行后，CPU可以重新上电，中断可以启用，CPU可以再次执行用户和操作系统进程。
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公开(公告)号：US06532151B2
公开(公告)日：2003-03-11
申请号：US09775164
申请日：2001-01-31
IPC分类号： H05K720
CPC分类号： G06F11/004 , G06F1/206 , G06F11/20 , H05K7/20836
摘要： An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, this operation may clear the obstruction. The fan may also be reversed to attempt to blow the obstruction clear of the fan. Thereafter, the fan is returned to normal operation and is monitored to determine whether the obstruction was removed. If the fan is still obstructed, these steps can be repeated. If the attempts to clear the obstruction are unsuccessful, then the computer system operator or management software can be signaled.
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