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    Non-volatile memory device and method of fabricating the same
    31.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07812375B2

    公开(公告)日：2010-10-12

    申请号：US11734659

    申请日：2007-04-12

    Applicant: Chang-Hyun Lee ,  Tea-Kwang Yu ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Byeong-In Choe

    Inventor： Chang-Hyun Lee ,  Tea-Kwang Yu ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Byeong-In Choe

    IPC: H01L31/112 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541

    Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.

    Abstract translation: 在非易失性存储器件中，第一隔离层形成为具有从半导体衬底的上表面具有预定深度的多个凹部。 翅片型第一有源区由第一隔离层限定，并且在其侧壁处具有从第一隔离层露出的一个或多个弯曲部分，其中第一有源区被折弯部分分成上部和下部， 上部的宽度比下部的宽度窄。 隧道绝缘层形成在第一有源区上。 在隧道绝缘层上形成存储节点层。 此外，在存储节点层上形成隔离绝缘层，并且在阻挡绝缘层上形成控制栅电极。

    Memory device and method of operating and fabricating the same
    32.
    发明申请
    Memory device and method of operating and fabricating the same 有权
    存储器件及其操作和制造方法

    公开(公告)号：US20100157668A1

    公开(公告)日：2010-06-24

    申请号：US12659159

    申请日：2010-02-26

    Applicant: Chang-Hyun Lee ,  Byeong-In Choi

    Inventor： Chang-Hyun Lee ,  Byeong-In Choi

    IPC: G11C16/00 ,  H01L29/788

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

    Abstract translation: 一种存储晶体管，包括衬底，衬底上的隧道绝缘图案，隧道绝缘图案上的电荷存储图案，电荷存储图案上的阻挡绝缘图案，以及阻挡绝缘图案上的栅电极，阻挡绝缘图案周围 栅电极及其操作和制造方法。 非易失性存储器还可以包括串联的多个存储晶体管和多个单元晶体管中的每一个之间的多个辅助结构。 多个辅助结构中的每一个可以是虚拟掩模图案或辅助栅极结构。

    Nonvolatile Memory Devices Having a Fin Shaped Active Region
    33.
    发明申请
    Nonvolatile Memory Devices Having a Fin Shaped Active Region 失效
    具有鳍形活动区域的非易失性存储器件

    公开(公告)号：US20090294837A1

    公开(公告)日：2009-12-03

    申请号：US12536740

    申请日：2009-08-06

    Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC: H01L29/792 ,  H01L29/78

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

    Abstract translation: 非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。 翅片形有源区形成在器件隔离层的各部分之间。 侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。 因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。 侧壁保护层可以使用器件隔离层形成。 或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

    NON-VOLATILE MEMORY DEVICES HAVING A MULTI-LAYERED CHARGE STORAGE LAYER
    35.
    发明申请
    NON-VOLATILE MEMORY DEVICES HAVING A MULTI-LAYERED CHARGE STORAGE LAYER 有权
    具有多层电荷存储层的非易失性存储器件

    公开(公告)号：US20090250747A1

    公开(公告)日：2009-10-08

    申请号：US12422862

    申请日：2009-04-13

    Applicant: Chang-Hyun Lee ,  Kyu-Charn Park

    Inventor： Chang-Hyun Lee ,  Kyu-Charn Park

    IPC: H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

    Abstract translation: 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

    Memory device and method of operating and fabricating the same
    38.
    发明申请
    Memory device and method of operating and fabricating the same 有权
    存储器件及其操作和制造方法

    公开(公告)号：US20080106934A1

    公开(公告)日：2008-05-08

    申请号：US11898252

    申请日：2007-09-11

    Applicant: Chang-Hyun Lee ,  Byeong-In Choi

    Inventor： Chang-Hyun Lee ,  Byeong-In Choi

    IPC: H01L29/788 ,  G11C11/40 ,  H01L21/3205

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

    Abstract translation: 一种存储晶体管，包括衬底，衬底上的隧道绝缘图案，隧道绝缘图案上的电荷存储图案，电荷存储图案上的阻挡绝缘图案，以及阻挡绝缘图案上的栅电极，阻挡绝缘图案周围 栅电极及其操作和制造方法。 非易失性存储器还可以包括串联的多个存储晶体管和多个单元晶体管中的每一个之间的多个辅助结构。 多个辅助结构中的每一个可以是虚拟掩模图案或辅助栅极结构。

    Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same
    39.
    发明申请
    Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same 有权
    具有多层电荷存储层的非易失性存储器件及其形成方法

    公开(公告)号：US20070284645A1

    公开(公告)日：2007-12-13

    申请号：US11799685

    申请日：2007-05-02

    Applicant: Chang-Hyun Lee ,  Kyu-Charn Park

    Inventor： Chang-Hyun Lee ,  Kyu-Charn Park

    IPC: G11C7/00

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

    Abstract translation: 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

    Flash memory devices including a pass transistor
    40.
    发明授权
    Flash memory devices including a pass transistor 有权
    包括传输晶体管的闪存器件

    公开(公告)号：US07271436B2

    公开(公告)日：2007-09-18

    申请号：US11021232

    申请日：2004-12-23

    Applicant: Chang-Hyun Lee ,  Sang-Pil Sim ,  Seung-Keun Lee

    Inventor： Chang-Hyun Lee ,  Sang-Pil Sim ,  Seung-Keun Lee

    IPC: H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/00

    CPC classification number: H01L27/11546 ,  H01L27/105 ,  H01L27/11526 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    Abstract: Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

    Abstract translation: 闪存集成电路器件包括集成电路基板。 集成电路基板上的单元阵列包括多个单元晶体管。 位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。 第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。 一个或多个第二传输晶体管耦合到第一传输晶体管。 第二传输晶体管具有第二扩散结构。 第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

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