公开(公告)号：US20080185568A1

公开(公告)日：2008-08-07

申请号：US12010921

申请日：2008-01-31

Applicant: Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

Inventor： Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C2213/79

Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

Abstract translation: 示例性实施例提供了使用电阻元件的非易失性存储器件。 非易失性存储器件可以包括半导体衬底，半导体衬底上的多个可变电阻图案以及与可变电阻图案相平行并耦合到接地电压的多个散热器图案。

公开(公告)号：US20070048924A1

公开(公告)日：2007-03-01

申请号：US11505355

申请日：2006-08-17

Applicant: In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

Inventor： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

IPC: H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Abstract translation: 制造非易失性存储器件的方法可以包括在半导体衬底上形成分离的浮置栅极，在半导体衬底上形成控制栅极，在半导体衬底的表面上保形地形成缓冲膜，将离子注入半导体衬底 浮置栅极，形成与各对浮置栅极的每个浮置栅极部分重叠的共同源极区域，在缓冲膜上沉积绝缘膜，在浮置栅极和控制栅极的侧壁处蚀刻缓冲膜和绝缘膜 在浮置栅极和控制栅极的侧壁处形成间隔物，并且在除了形成公共源极区域的控制栅极的一侧之外的控制栅极的一侧的半导体衬底中形成漏极区域。

公开(公告)号：US07094646B2

公开(公告)日：2006-08-22

申请号：US11119801

申请日：2005-05-03

Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

公开(公告)号：US06924505B2

公开(公告)日：2005-08-02

申请号：US10858926

申请日：2004-06-02

Applicant: Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

Inventor： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L23/58

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract translation: 具有提高测量可靠性的测量图案的半导体器件以及使用测量图案测量半导体器件的方法。 半导体器件包括具有形成集成电路的芯片面积的半导体衬底和围绕芯片区域的划线区域。 半导体器件还包括形成在划线区域中的测量图案，并具有包括测量光束投射的光束区域的表面截面面积和形成在测量图案中的虚拟图案，以减小测量图案的表面截面面积 。 虚拟图案的表面截面积占射束面积的表面截面面积的约5％至约15％。

公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

Applicant: Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

Inventor： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract translation: 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。