公开(公告)号：US20050012087A1

公开(公告)日：2005-01-20

申请号：US10619828

申请日：2003-07-15

Applicant: Yi-Ming Sheu ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Chung-Cheng Wu

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/26533 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A transistor device having a strained channel and a method for forming the transistor device are disclosed. The transistor device includes a semiconductor region having a top surface. The transistor device includes a source region, a drain region, and a channel region in the semiconductor region. The channel region is between the source region and the drain region. The transistor device includes an oxide region within the channel region and a gate overlying the channel region. The oxide region is laterally spaced from the source and drain regions. The transistor device includes a gate dielectric between the gate and the channel region.

Abstract translation: 公开了具有应变通道的晶体管器件和用于形成晶体管器件的方法。 晶体管器件包括具有顶表面的半导体区域。 晶体管器件包括半导体区域中的源极区域，漏极区域和沟道区域。 沟道区域在源极区域和漏极区域之间。 晶体管器件包括沟道区域内的氧化物区域和覆盖沟道区域的栅极。 氧化物区域与源极区域和漏极区域横向间隔开。 晶体管器件包括在栅极和沟道区域之间的栅极电介质。

公开(公告)号：US06583014B1

公开(公告)日：2003-06-24

申请号：US10246251

申请日：2002-09-18

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01K21336

CPC classification number: H01L29/42392 ,  H01L29/0657 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract translation: 水平周围栅极MOSFET包括形成在半导体衬底的上硅层中的整体结构，其基本上是绝缘体上硅（SOI）晶片，所述整体结构包括相对地设置在圆柱形 通道区域纵向设置在源极和漏极之间。 通道被栅极电介质覆盖，并且环形栅电极沿周向覆盖通道。

公开(公告)号：US06175394B1

公开(公告)日：2001-01-16

申请号：US08760101

申请日：1996-12-03

Applicant: Chung-Cheng Wu ,  Wen-Jyh Sah

Inventor： Chung-Cheng Wu ,  Wen-Jyh Sah

IPC: G02F1136

CPC classification number: H01L29/78696 ,  G02F1/136204 ,  H01L27/12

Abstract: A flat panel display includes a plurality of parallel row select lines and a plurality of column drive lines, with the row select lines and the column drive lines intersecting to define a matrix of pixel locations. Signals are provided to contact pads located on the periphery of the display and the signals flow over the row select lines and the column drive lines to thin film transistors located adjacent a pixel electrode at each of the pixel locations. The signals provided to each thin film transistor cause the transistor to charge a corresponding pixel electrode to control a pixel of the display. ESD protection for the display comprises a guard ring adjacent the contact pads. Capacitively coupled field effect transistors (CCFETs) connect the row select lines to the guard ring and connect the column drive lines to the guard ring. A CCFET is formed as a thin film transistor and typically has a floating gate capacitively coupled to the drain and source of the thin film transistor.

Abstract translation: 平板显示器包括多个平行的行选择线和多个列驱动线，其中行选择线和列驱动线相交以限定像素位置的矩阵。 信号被提供给位于显示器周边的接触焊盘，并且信号流过行选择线和列驱动线到位于每个像素位置处的像素电极附近的薄膜晶体管。 提供给每个薄膜晶体管的信号导致晶体管对相应的像素电极充电以控制显示器的像素。 用于显示器的ESD保护包括与接触垫相邻的保护环。 电容耦合场效应晶体管（CCFET）将行选择线连接到保护环，并将列驱动线连接到保护环。 CCFET形成为薄膜晶体管，并且通常具有电容耦合到薄膜晶体管的漏极和源极的浮动栅极。

公开(公告)号：US6164562A

公开(公告)日：2000-12-26

申请号：US449909

申请日：1999-12-02

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: B05B3/04

CPC classification number: B05B3/0436 ,  Y10T137/86847

Abstract: A rotary type swingable sprayer comprising a fixing tube head, a rotatable tube head, and a nozzle tube. The rotatable tube head is installed atop the fixing tube head, and the nozzle tube is installed atop the rotatable tube head. The lower end of the fixing tube head is connected with a water tube for guiding water. When water flows through the rotatable tube head, the rotatable tube head will swing nearly a full cycle repeatedly so as to drive the nozzle tube above to swing repeatedly. Thus, water is jetted out from the distal end of the nozzle tube. Therefore, water is sprayed out nearly through a full cycle in the whole area.

Abstract translation: 一种旋转式可摆动喷雾器，包括固定管头，可旋转管头和喷嘴管。 可旋转管头安装在固定管头的顶部，喷嘴管安装在可旋转管头的顶部。 固定管头的下端与用于引导水的水管连接。 当水流过可旋转的管头时，可旋转的管头将重复地摆动几乎整个周期，以便将喷嘴管驱动到上方以重复摆动。 因此，从喷嘴管的远端喷出水。 因此，在整个地区几乎完全喷洒水。

公开(公告)号：US5920780A

公开(公告)日：1999-07-06

申请号：US791870

申请日：1997-01-31

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/316 ,  H01L21/60 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/316

Abstract: The present invention relates to a method of forming a self-aligned contact (SAC) window employing the liquid phase deposition (LPD) that allows low temperature deposition and selective growing of a LPD-SiO.sub.2 film as a stress-buffer layer to prevent WSi peeling during the formation of the SAC window. Specifically, the method comprises the steps of forming a nitride cap and a gate consisting of a WSi layer and a polysilicon layer over a surface of a silicon substrate followed by the formation of the sources and drain regions on the silicon substrate as well as by the process of forming the LPD-SiO.sub.2 film. A nitride spacer is formed at a sidewall of the nitride cap and the gate, and the SAC window is then formed by depositing a dielectric layer such as a SiO.sub.2 layer followed by exposing through a mask.

Abstract translation: 本发明涉及一种使用液相沉积（LPD）形成自对准接触（SAC）窗口的方法，其允许低温沉积和LPD-SiO 2膜的选择性生长作为应力缓冲层以防止WSi剥离 在SAC窗口的形成期间。 具体地，该方法包括以下步骤：在硅衬底的表面上形成氮化物帽和由WSi层和多晶硅层组成的栅极，随后在硅衬底上形成源区和漏区，以及由 形成LPD-SiO2膜的工艺。 在氮化物盖和栅极的侧壁处形成氮化物间隔物，然后通过沉积诸如SiO 2层的介电层然后通过掩模曝光来形成SAC窗口。

公开(公告)号：US5444411A

公开(公告)日：1995-08-22

申请号：US248350

申请日：1994-05-24

Applicant: Ming T. Yang ,  Chung-Cheng Wu

Inventor： Ming T. Yang ,  Chung-Cheng Wu

IPC: G06G7/14 ,  G06G7/42 ,  H03K17/62

CPC classification number: G06G7/14

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract translation: 使用电容器形成其输入的加权和的阈值电路使用两级电容器结构。 这两个阶段形成一个紧凑的结构，增加了可以处理的输入信号的数量，并增加了将权重分配给输入信号的灵活性。 用于输入信号的电容器电极被布置成两组，并且每组的电极被静电耦合到第一和第二电极。 分别从第一和第二电极延伸的第三和第四电极静电耦合到其电压相加的第五和第六电极的整体结构。 第五和第六电极导电地连接到FET阈值电路的栅极，其响应加权和相加的输入信号。

公开(公告)号：US5350700A

公开(公告)日：1994-09-27

申请号：US160243

申请日：1993-12-02

Applicant: Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: H01L21/331 ,  H01L21/74 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/74

Abstract: A method of fabricating a bipolar transistor with a buried subcollector by forming a collector layer and a base layer in a semiconductor substrate. A polysilicon layer is deposited over the base layer and spaced emitter and base contact regions formed in the base layer. A mask is formed over the emitter and base contact regions and the substrate anisotropically etched to form pedestals with vertical sidewalls. A masking layer is formed on the vertical sidewalls, and a large angle ion implant used to introduce ions beneath the collector layer, thereby forming a subcollector region.

Abstract translation: 一种通过在半导体衬底中形成集电极层和基极层来制造具有掩埋子集电极的双极晶体管的方法。 在基底层上沉积多晶硅层，并且在基底层中形成间隔开的发射极和基极接触区域。 在发射极和基极接触区域上形成掩模，并且各向异性蚀刻衬底以形成具有垂直侧壁的基座。 掩模层形成在垂直侧壁上，并且大角度离子注入用于将离子引入集电极层下面，从而形成子集电极区域。

公开(公告)号：US20110291200A1

公开(公告)日：2011-12-01

申请号：US13086186

申请日：2011-04-13

Applicant: Ali KESHAVARZI ,  Ta-Pen GUO ,  Helen Shu-Hui CHANG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Shu-Min CHEN ,  Min CAO ,  Yung-Chin HOU

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Helen Shu-Hui CHANG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Shu-Min CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract translation: 集成电路包括用于第一类型晶体管的第一扩散区域。 第一类型晶体管包括第一漏极区域和第一源极区域。 用于第二类型晶体管的第二扩散区域与第一扩散区域分离。 第二类型晶体管包括第二漏极区域和第二源极区域。 栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。 第一金属结构与第一源区电耦合。 第二金属结构与第二漏区电耦合。 第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。 第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07378889B2

公开(公告)日：2008-05-27

申请号：US11282585

申请日：2005-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H03K7/08

CPC classification number: H02M3/33507 ,  H02M2001/0032 ,  H03K3/00 ,  H03K17/00 ,  H03K17/0822 ,  Y02B70/16

Abstract: A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis comparison circuit extracting a feedback voltage, a high threshold voltage and a low threshold voltage, and the voltages are executed by a comparison and hysteresis operation to a output blanking signal, a PWM control unit extracting a detecting current signal and the feedback voltage to output a modulation signal after a comparison operation is executed; an OR gate circuit connected to the hysteresis comparison circuit and the PWM control unit for receiving the blanking signal and the modulation signal to output a reset signal; and a synchronization signal output unit connected to the OR gate circuit for receiving the reset signal and an oscillation signal to output the drive signal.

Abstract translation: 在电源中使用具有由输出电压反馈滞后电路控制的省电模式的脉宽调制装置。 本发明包括提取反馈电压，高阈值电压和低阈值电压的滞后比较电路，并且通过对输出消隐信号进行比较和滞后操作来执行电压，PWM控制单元提取检测电流信号，以及 在执行比较操作之后输出调制信号的反馈电压; 连接到迟滞比较电路的OR门电路和用于接收消隐信号和调制信号以输出复位信号的PWM控制单元; 以及连接到或门电路的同步信号输出单元，用于接收复位信号和振荡信号以输出驱动信号。