公开(公告)号：US20050012087A1

公开(公告)日：2005-01-20

申请号：US10619828

申请日：2003-07-15

申请人： Yi-Ming Sheu ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Chung-Cheng Wu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/26533 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

摘要： A transistor device having a strained channel and a method for forming the transistor device are disclosed. The transistor device includes a semiconductor region having a top surface. The transistor device includes a source region, a drain region, and a channel region in the semiconductor region. The channel region is between the source region and the drain region. The transistor device includes an oxide region within the channel region and a gate overlying the channel region. The oxide region is laterally spaced from the source and drain regions. The transistor device includes a gate dielectric between the gate and the channel region.

摘要翻译： 公开了具有应变通道的晶体管器件和用于形成晶体管器件的方法。 晶体管器件包括具有顶表面的半导体区域。 晶体管器件包括半导体区域中的源极区域，漏极区域和沟道区域。 沟道区域在源极区域和漏极区域之间。 晶体管器件包括沟道区域内的氧化物区域和覆盖沟道区域的栅极。 氧化物区域与源极区域和漏极区域横向间隔开。 晶体管器件包括在栅极和沟道区域之间的栅极电介质。

公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07071515B2

公开(公告)日：2006-07-04

申请号：US10619114

申请日：2003-07-14

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US20060079068A1

公开(公告)日：2006-04-13

申请号：US11288858

申请日：2005-11-29

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/76

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

公开(公告)号：US20050012173A1

公开(公告)日：2005-01-20

申请号：US10619114

申请日：2003-07-14

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/337 ,  H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US08354718B2

公开(公告)日：2013-01-15

申请号：US11751959

申请日：2007-05-22

申请人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

发明人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

IPC分类号： H01L21/02

CPC分类号： H01L29/1083 ,  H01L29/66636

摘要： An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

摘要翻译： 一种装置，包括第一掺杂剂型和第一掺杂剂浓度的衬底; 并且具有大于第一掺杂剂浓度的第一掺杂剂类型和第二掺杂剂浓度; 在所述衬底上方的栅堆叠，并且在所述袋区域之间横向; 第一和第二源极/漏极区域在栅极堆叠的相对侧上并且垂直地在栅极堆叠层与凹穴区域之间，第一和第二源极/漏极区域具有与第一掺杂剂类型相反的第二掺杂剂类型和第三掺杂剂浓度; 以及具有大于第三掺杂剂浓度的第二掺杂剂类型和第四掺杂剂浓度的第三和第四源极/漏极区域，其中所述穴状区域在第三和第四源极/漏极区域之间，并且第三和第四源极/漏极 区域在第一和第二源极/漏极区域之间以及基板的主体部分之间是垂直的。

公开(公告)号：US06703187B2

公开(公告)日：2004-03-09

申请号：US10043861

申请日：2002-01-09

申请人： Yi-Ming Sheu ,  Fu-Liang Yang

发明人： Yi-Ming Sheu ,  Fu-Liang Yang

IPC分类号： G03F726

CPC分类号： H01L21/823892 ,  H01L21/823878

摘要： An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.

摘要翻译： 一种用于形成用于CMOS半导体器件的自对准双阱结构的改进方法，包括提供用于在其中形成双阱结构的衬底; 在所述衬底上形成注入掩模层以包括工艺表面，所述掩模层被图案化以暴露所述工艺表面的第一部分以用于注入离子; 使处理表面的第一部分经受第一离子注入工艺以形成包括在衬底中的第一掺杂区; 形成植入阻挡层，所述植入物阻挡层包括在所述过程表面的所述第一部分上可选择地蚀刻到所述植入物掩模层的材料; 去除所述植入物掩模层以暴露所述工艺表面的第二部分; 以及对所述工艺表面的第二部分进行第二离子注入工艺以形成邻近所述第一掺杂区域设置的第二掺杂区域。

公开(公告)号：US07598130B2

公开(公告)日：2009-10-06

申请号：US11529091

申请日：2006-09-28

申请人： Chung-Heng Yang ,  Yi-Ming Sheu ,  Sheng-Jier Yang

发明人： Chung-Heng Yang ,  Yi-Ming Sheu ,  Sheng-Jier Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/823493 ,  H01L21/2652 ,  H01L21/823892

摘要： A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the re-implantation blocking layer is exposed through the opening, performing an implantation to introduce an impurity into a portion of the semiconductor substrate underlying the opening to form a well region, removing the mask, and removing the re-implantation blocking layer.

摘要翻译： 一种用于形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成再注入阻挡层，在重新注入阻挡层上形成掩模，图案化掩模以形成开口，其中一部分re 通过开口暴露植入阻挡层，进行注入以将杂质引入到开口下方的半导体衬底的一部分中以形成阱区，去除掩模，以及去除重新注入阻挡层。

公开(公告)号：US07545001B2

公开(公告)日：2009-06-09

申请号：US10722218

申请日：2003-11-25

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Lun Cheng ,  Yi-Ming Sheu

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Lun Cheng ,  Yi-Ming Sheu

IPC分类号： H01L23/62

CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices includes one of: (1) first source/drain regions recessed within the surface; and (2) first source/drain regions extending from the surface. A second one of the NMOS and PMOS devices includes one of: (1) second source/drain regions recessed within the surface wherein the first source/drain regions extend from the surface; (2) second source/drain regions extending from the surface wherein the first source/drain regions are recessed within the surface; and (3) second source/drain regions substantially coplanar with the surface.

摘要翻译： 包括位于衬底中的隔离区域的半导体器件，部分地位于衬底的表面上的NMOS器件以及通过隔离区域与NMOS器件隔离并且部分地位于表面上的PMOS器件。 NMOS和PMOS器件中的第一个包括以下之一：（1）凹陷在表面内的第一源极/漏极区域; 和（2）从表面延伸的第一源极/漏极区域。 NMOS和PMOS器件中的第二个包括以下之一：（1）凹陷在表面内的第二源极/漏极区域，其中第一源极/漏极区域从表面延伸; （2）从表面延伸的第二源极/漏极区域，其中第一源极/漏极区域在表面内凹陷; 和（3）基本上与表面共面的第二源极/漏极区域。

公开(公告)号：US20080290380A1

公开(公告)日：2008-11-27

申请号：US11753374

申请日：2007-05-24

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Shyh-Wei Wang

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Shyh-Wei Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a substrate and a gate formed on the substrate. A gate spacer is formed next to the gate. The gate spacer has a height greater than the height of the gate. A method of forming a semiconductor device includes providing a substrate with a gate layer. A hard mask layer is formed over the gate layer, and both layers are then etched using a pattern, forming a gate and a hard mask. A spacer layer is then deposited over the substrate, gate, and hard mask. The spacer layer is etched to form a gate spacer next to the gate. The hard mask is then removed.

摘要翻译： 半导体器件包括衬底和形成在衬底上的栅极。 在栅极旁边形成栅极间隔物。 栅极间隔物的高度大于栅极的高度。 形成半导体器件的方法包括：提供具有栅极层的衬底。 在栅极层上形成硬掩模层，然后使用图案蚀刻两层，形成栅极和硬掩模。 然后将间隔层沉积在衬底，栅极和硬掩模上。 蚀刻间隔层以在栅极附近形成栅极间隔。 然后去除硬面罩。