公开(公告)号：US08275328B2

公开(公告)日：2012-09-25

申请号：US13053491

申请日：2011-03-22

Applicant: In Kwang Kim ,  Hong Woo Lee

Inventor： In Kwang Kim ,  Hong Woo Lee

IPC: H04B7/02

CPC classification number: H04B7/0689 ,  H04B7/0871

Abstract: A mobile phone to transmit and receive a radio frequency signal through a first antenna and a second antenna in a radio communication system includes a first radio frequency signal receiving unit to convert the radio frequency signal received through the first antenna into a baseband signal to be transmitted to a controller, a second radio frequency signal receiving unit to convert the radio frequency signal received through the second antenna into a baseband signal to be transmitted to the controller, and a radio frequency signal transmitting unit to convert a baseband signal transmitted from the controller into a radio frequency signal, to distribute the radio frequency signal, and to selectively output the distributed radio frequency signal to the first antenna and the second antenna.

Abstract translation: 一种在无线电通信系统中通过第一天线和第二天线发送和接收射频信号的移动电话包括：第一射频信号接收单元，用于将通过第一天线接收的射频信号转换为要传输的基带信号 控制器，第二射频信号接收单元，将通过第二天线接收的射频信号转换为要发送到控制器的基带信号;以及射频信号发送单元，将从控制器发送的基带信号转换为 射频信号，以分配射频信号，并选择性地将分布式射频信号输出到第一天线和第二天线。

公开(公告)号：US08194026B2

公开(公告)日：2012-06-05

申请号：US11782957

申请日：2007-07-25

Applicant: Hong-Woo Lee ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim

Inventor： Hong-Woo Lee ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2320/02 ,  G09G2330/08 ,  G11C19/28

Abstract: A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.

Abstract translation: 栅极驱动器包括具有连接在一起的多个级的移位寄存器，并将包括第一脉冲和第二脉冲的门信号输出到栅极线。 舞台包括保持部分，预充电部分，上拉部分和下拉部分。 保持部分响应于第一时钟信号将输出端子放电到截止电压。 预充电部件关闭保持部件，并响应于前一级的输出信号将第一时钟信号作为第一脉冲输出到输出端子。 上拉部分响应于前一级的输出信号，将第二时钟信号作为第二脉冲输出到输出端。 下拉部分响应于下一级的输出信号将第一输出端子放电到截止电压。

公开(公告)号：US08178697B2

公开(公告)日：2012-05-15

申请号：US12864139

申请日：2008-04-25

Applicant: Soon Kil Ahn ,  Hong-Woo Lee ,  Choong Leol Yoo ,  Young-Min Kim ,  Chang Geun Song ,  Sung Kwun Kang ,  Jun A. You ,  Bong Kwan Soh ,  Dong Hyuk Nam

Inventor： Soon Kil Ahn ,  Hong-Woo Lee ,  Choong Leol Yoo ,  Young-Min Kim ,  Chang Geun Song ,  Sung Kwun Kang ,  Jun A. You ,  Bong Kwan Soh ,  Dong Hyuk Nam

IPC: C07F5/02 ,  C07D207/335

CPC classification number: C07D207/34 ,  C07F5/025

Abstract: The present invention relates to a novel method for preparing atorvastatin. According to the present invention, provided are a novel intermediate of the preparation of atorvastatin and a method of preparing large amounts of atorvastatin in a safe manner using the intermediate.

Abstract translation: 本发明涉及一种制备阿托伐他汀的新方法。 根据本发明，提供了阿托伐他汀制剂的新型中间体和使用该中间体以安全的方式制备大量阿托伐他汀的方法。

公开(公告)号：US20110267326A1

公开(公告)日：2011-11-03

申请号：US12898090

申请日：2010-10-05

Applicant: Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

Inventor： Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

IPC: G09G5/00 ,  H03K3/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal. Each stage of the plurality of stages includes; a voltage output part which outputs the gate voltage, an output driving part which drives the voltage output part, a holding part which holds the gate line at an off-voltage, and a discharge part arranged at a first end of the gate line to discharge the gate line to the off-voltage in response to the gate voltage output from the voltage output part,

Abstract translation: 栅极驱动电路包括多个级彼此连接并且多级的每一级响应于至少一个时钟信号而将栅极电压输出到多条栅极线的对应栅极线。 多个阶段的每个阶段包括： 输出栅极电压的电压输出部分，驱动电压输出部分的输出驱动部分，将栅极线保持在截止电压的保持部分和布置在栅极线的第一端以放电的放电部分 所述栅极线响应于从所述电压输出部输出的栅极电压而断开所述截止电压，

公开(公告)号：US07911436B2

公开(公告)日：2011-03-22

申请号：US11535524

申请日：2006-09-27

Applicant: Hong-Woo Lee ,  Kye-Hun Lee ,  Jong-Hwan Lee

Inventor： Hong-Woo Lee ,  Kye-Hun Lee ,  Jong-Hwan Lee

IPC: G09G3/36 ,  G11C19/00 ,  H03K19/01

CPC classification number: G09G3/3677 ,  G09G2300/0439 ,  G09G2310/0281 ,  G09G2310/0286 ,  G11C19/184

Abstract: A shift register includes a plurality of stages connected to one another to sequentially generate output signals. Each of the stages has a plurality of output terminals, and each of the output terminals is connected to at least two gate lines and outputs a first output voltage alternately to the at least two gate lines to turn on thin film transistors.

Abstract translation: 移位寄存器包括彼此连接的多个级，以顺序地产生输出信号。 每个级具有多个输出端子，并且每个输出端子连接到至少两条栅极线并且交替地向至少两个栅极线输出第一输出电压以导通薄膜晶体管。

公开(公告)号：US07876731B2

公开(公告)日：2011-01-25

申请号：US11321239

申请日：2005-12-29

Applicant: Woo-Jin Jang ,  Hong-Woo Lee

Inventor： Woo-Jin Jang ,  Hong-Woo Lee

IPC: H04B7/216

CPC classification number: H04B1/70735

Abstract: Disclosed herein are a method and apparatus for acquiring a code group in an asynchronous Wideband Code Division Multiple Access (WCDMA) system. A primary synchronization channel search unit achieves primary synchronization channel slot timing synchronization. Then, the 1-1 search unit and 1-2 search unit of a secondary synchronization channel receive secondary synchronization channels from first and second antennas, respectively, start correlation operations between some of the slots of the received channels and code group candidates, and transmit information about candidates having values exceeding a predetermined threshold value to a determination unit. The determination unit transmits the received information about candidates to a second search unit of the secondary synchronization channel. The second search unit of the secondary synchronization channel calculates correlation characteristics based on the received information about candidates and selects a code group candidate having a highest correlation characteristic.

Abstract translation: 本文公开了一种用于在异步宽带码分多址（WCDMA）系统中获取码组的方法和装置。 主同步信道搜索单元实现主同步信道时隙定时同步。 然后，次同步信道的1-1搜索单元和1-2搜索单元分别从第一和第二天线接收辅同步信道，开始接收信道的一些时隙和码组候选之间的相关操作，并发送 关于具有超过预定阈值的值的候选的信息给确定单元。 确定单元将接收到的关于候选的信息发送到辅同步信道的第二搜索单元。 次同步信道的第二搜索单元基于所接收的关于候选的信息计算相关特性，并选择具有最高相关特性的码组候选。

公开(公告)号：US20100188361A1

公开(公告)日：2010-07-29

申请号：US12616717

申请日：2009-11-11

Applicant: Sung-Man Kim ,  Beom-Jun Kim ,  Sun-Kyu Joo ,  Hong-Woo Lee

Inventor： Sung-Man Kim ,  Beom-Jun Kim ,  Sun-Kyu Joo ,  Hong-Woo Lee

IPC: G06F3/044 ,  H01J9/00

CPC classification number: G02F1/136286 ,  G02F1/13338 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/40

Abstract: A display panel and a method of manufacturing the same are provided, which can prevent the deterioration of input sensitivity to the panel, and maximize the aperture ratio of the panel. The display panel includes a first substrate, a gate line and a data line crossing each other on the first substrate, in a manner that the gate line and the data line are electrically insulated from each other. The display panel further comprises a first sensor wire formed in parallel to the data line, a second sensor wire formed to overlap the data line in parallel to the data line, a second substrate arranged opposite to the first substrate, and a sensor spacer formed on the second substrate to project toward the first substrate.

Abstract translation: 提供了一种显示面板及其制造方法，可以防止对面板的输入灵敏度的劣化，并使面板的开口率最大化。 显示面板包括在栅极线和数据线彼此电绝缘的方式在第一衬底上彼此交叉的第一衬底，栅极线和数据线。 显示面板还包括与数据线平行地形成的第一传感器线，与数据线平行地形成为与数据线重叠的第二传感器线，与第一基板相对布置的第二基板和形成在第一基板上的传感器间隔件 第二基板朝向第一基板突出。

公开(公告)号：US20100156954A1

公开(公告)日：2010-06-24

申请号：US12604692

申请日：2009-10-23

Applicant: Sung-Man KIM ,  Hong-Woo LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Jong-Hyuk LEE

Inventor： Sung-Man KIM ,  Hong-Woo LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Jong-Hyuk LEE

IPC: G09G5/10

CPC classification number: G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0465 ,  G09G2300/0809 ,  G09G2310/0202 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/0666

Abstract: A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.

Abstract translation: 显示装置包括：多个像素块，所述多个像素块中的每个像素块包括连接到第一开关元件的第一像素电极和连接到第二开关元件的第二像素电极; 栅极线，沿着第一方向延伸并且包括连接到第一开关元件的第一栅极线和连接到第二开关元件的第二栅极线; 以及沿着与第一方向相交的第二方向延伸的数据线。 栅极电压施加到第二栅极线之前的第一栅极线，并且每个像素块的第一像素电极显示相同的颜色。

公开(公告)号：US20090190082A1

公开(公告)日：2009-07-30

申请号：US12181678

申请日：2008-07-29

Applicant: Hong-Woo Lee ,  Jong-Oh Kim ,  Sung-Man Kim ,  Sun-Kyu Joo ,  Bong-Jun Lee ,  Jae-Min Shin

Inventor： Hong-Woo Lee ,  Jong-Oh Kim ,  Sung-Man Kim ,  Sun-Kyu Joo ,  Bong-Jun Lee ,  Jae-Min Shin

IPC: G02F1/1343

CPC classification number: G02F1/136213

Abstract: A display substrate includes a first switching element, a second switching element, a first pixel electrode, a second pixel electrode, a main storage electrode and a sub-storage electrode. The first switching element is connected to a data line and a first gate line. The second switching element is connected to the data line and a second gate line adjacent to the first gate line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The main storage electrode is disposed in an area between the first pixel electrode and the second electrode to overlap with first ends of the first and second pixel electrodes. The sub-storage electrode is spaced apart from the first and second gate lines.

Abstract translation: 显示基板包括第一开关元件，第二开关元件，第一像素电极，第二像素电极，主存储电极和副存储电极。 第一开关元件连接到数据线和第一栅极线。 第二开关元件连接到数据线和与第一栅极线相邻的第二栅极线。 第一像素电极电连接到第一开关元件。 第二像素电极电连接到第二开关元件。 主存储电极设置在第一像素电极和第二电极之间的区域中，以与第一和第二像素电极的第一端重叠。 副存储电极与第一和第二栅极线间隔开。

公开(公告)号：US20090189677A1

公开(公告)日：2009-07-30

申请号：US12241880

申请日：2008-09-30

Applicant: Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

Inventor： Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

IPC: H03K17/687 ,  G09G5/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

Abstract translation: 门驱动电路包括级级，级联级，每级包括：在水平扫描周期（1H）期间将门电压上拉至时钟信号的上拉部分; 在水平扫描期间（1H）中将进位电压拉入时钟信号的进位部分; 上拉驱动部分连接到与进位部分和上拉部分共同的控制端子（Q-节点），并且从上一级接收先前的进位电压以接通上拉部分和进位 部分; 以及纹波防止部，其基于在所述进位部和所述上拉部的所述Q节点处产生的波纹来防止在前一级的前一Q点产生的纹波。