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    Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the same
    3.
    发明授权
    Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the same 有权
    监测用于蚀刻工艺的测试元件组（TEG）和使用其制造半导体器件的方法

    公开(公告)号：US08697455B2

    公开(公告)日：2014-04-15

    申请号：US13415270

    申请日：2012-03-08

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Woo-Jin Jang

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Woo-Jin Jang

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

    摘要翻译： 公开了一种用于半导体器件中的蚀刻工艺的监测TEG。 TEG包括衬底上的蚀刻停止层和设置在蚀刻停止层上的要蚀刻的靶层。 要蚀刻的目标层包括通过蚀刻待蚀刻的目标层的一部分形成的第一开口部分和通过蚀刻待蚀刻的目标层的另一部分而形成的第二开口部。 第二开口部的深度比第一开口部小。 可以测量通过第一部分蚀刻工艺形成的部分接触孔的深度。

    MONITORING TEST ELEMENT GROUPS (TEGS) FOR ETCHING PROCESS AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    4.
    发明申请
    MONITORING TEST ELEMENT GROUPS (TEGS) FOR ETCHING PROCESS AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 有权
    用于蚀刻过程的监测元件组（TEGS）和使用其制造半导体器件的方法

    公开(公告)号：US20120231564A1

    公开(公告)日：2012-09-13

    申请号：US13415270

    申请日：2012-03-08

    申请人： KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

    发明人： KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

    摘要翻译： 公开了一种用于半导体器件中的蚀刻工艺的监测TEG。 TEG包括衬底上的蚀刻停止层和设置在蚀刻停止层上的要蚀刻的靶层。 要蚀刻的目标层包括通过蚀刻待蚀刻的目标层的一部分形成的第一开口部分和通过蚀刻待蚀刻的目标层的另一部分而形成的第二开口部分。 第二开口部的深度比第一开口部小。 可以测量通过第一部分蚀刻工艺形成的部分接触孔的深度。

    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby
    5.
    发明授权
    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
    形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法

    公开(公告)号：US08232200B1

    公开(公告)日：2012-07-31

    申请号：US13051732

    申请日：2011-03-18

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    Apparatus and method for acquirying a preamble in an orthogonal frequency division multiple access mobile terminal
    6.
    发明授权
    Apparatus and method for acquirying a preamble in an orthogonal frequency division multiple access mobile terminal 有权
    用于在正交频分多址移动终端中获取前同步码的装置和方法

    公开(公告)号：US07869489B2

    公开(公告)日：2011-01-11

    申请号：US11694243

    申请日：2007-03-30

    申请人： Woo Jin Jang

    发明人： Woo Jin Jang

    IPC分类号： H04B1/00

    CPC分类号： H04L27/2656 ,  H04B1/70752 ,  H04B1/70775 ,  H04B2201/70707 ,  H04L7/043 ,  H04L27/2675

    摘要： A preamble acquisition apparatus includes a first PN code generation unit for generating a first PN code having a bit string, a first correlation calculation unit for correlating a received frequency domain preamble signal with the first PN code within a first correlation range to generate a first correlation value, a first correlation value comparison unit for comparing the first correlation value with a first threshold value, a second PN code generation unit for generating a second PN code, a second correlation calculation unit for correlating the received frequency domain preamble signal with the second PN code within a second correlation range to generate a second correlation value, and a preamble acquisition determination unit for comparing the second correlation value with a second threshold value to determine whether to acquire the preamble. The bit values of the first PN code are located in the second PN code.

    摘要翻译： 前导码获取装置包括：第一PN码产生单元，用于产生具有比特串的第一PN码;第一相关计算单元，用于将接收到的频域前导信号与第一相关范围内的第一PN码相关，以产生第一相关 第一相关值比较单元，用于将第一相关值与第一阈值进行比较;第二PN码产生单元，用于产生第二PN码;第二相关计算单元，用于将接收到的频域前导信号与第二PN 代码在第二相关范围内产生第二相关值，以及前导码获取确定单元，用于将第二相关值与第二阈值进行比较，以确定是否获取前导码。 第一PN码的位值位于第二PN码中。

    APPARATUS FOR ADJUSTING LEVEL OF REFRIGERATOR
    7.
    发明申请
    APPARATUS FOR ADJUSTING LEVEL OF REFRIGERATOR 有权
    调节冷藏水位的装置

    公开(公告)号：US20110001414A1

    公开(公告)日：2011-01-06

    申请号：US12865834

    申请日：2008-12-30

    申请人： Woo-Jin Jang

    发明人： Woo-Jin Jang

    IPC分类号： F25D23/02 ,  F16M11/24 ,  G08B21/00

    CPC分类号： F25D23/00 ,  F25D2323/0011

    摘要： An apparatus for adjusting the level of a refrigerator includes: a main body; a guide groove formed to be level in a forward/backward direction of the main body; a movement unit inserted in the guide groove and moving in the direction in which the main body is inclined; a contact point part formed at one of both ends of the guide groove and selectively connected to the movement unit; and a notifying unit informing about whether or not the contact point part is connected. When the refrigerator is installed, an installation technician can recognize whether or not the refrigerator is installed to be level regardless of a skilled degree of the installation technician, so the installation time can be shortened and a service satisfaction of consumers can be increased.

    摘要翻译： 一种用于调节冰箱水平的装置，包括：主体; 导向槽，其形成为在主体的前后方向上平坦; 移动单元，其插入所述引导槽并沿所述主体倾斜的方向移动; 接触点部分，其形成在所述引导槽的两端之一并且选择性地连接到所述移动单元; 以及通知单元，通知接点部分是否连接。 当安装冰箱时，无论安装技术人员的熟练程度如何，安装技术人员都可以识别冰箱是否安装成水平，因此可以缩短安装时间并且可以提高消费者的服务满意度。

    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby
    8.
    发明授权
    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
    形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法

    公开(公告)号：US08373273B2

    公开(公告)日：2013-02-12

    申请号：US13533135

    申请日：2012-06-26

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY
    9.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY 有权
    形成集成电路装置的方法，其具有金属扩散阻挡层和形成的器件的大分子互连

    公开(公告)号：US20120267785A1

    公开(公告)日：2012-10-25

    申请号：US13533135

    申请日：2012-06-26

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    Method and apparatus for acquiring code group in asynchronous wideband code division multiple access system using receiver diversity
    10.
    发明授权
    Method and apparatus for acquiring code group in asynchronous wideband code division multiple access system using receiver diversity 有权
    使用接收机分集的异步宽带码分多址系统中获取码组的方法和装置

    公开(公告)号：US07876731B2

    公开(公告)日：2011-01-25

    申请号：US11321239

    申请日：2005-12-29

    申请人： Woo-Jin Jang ,  Hong-Woo Lee

    发明人： Woo-Jin Jang ,  Hong-Woo Lee

    IPC分类号： H04B7/216

    CPC分类号： H04B1/70735

    摘要： Disclosed herein are a method and apparatus for acquiring a code group in an asynchronous Wideband Code Division Multiple Access (WCDMA) system. A primary synchronization channel search unit achieves primary synchronization channel slot timing synchronization. Then, the 1-1 search unit and 1-2 search unit of a secondary synchronization channel receive secondary synchronization channels from first and second antennas, respectively, start correlation operations between some of the slots of the received channels and code group candidates, and transmit information about candidates having values exceeding a predetermined threshold value to a determination unit. The determination unit transmits the received information about candidates to a second search unit of the secondary synchronization channel. The second search unit of the secondary synchronization channel calculates correlation characteristics based on the received information about candidates and selects a code group candidate having a highest correlation characteristic.

    摘要翻译： 本文公开了一种用于在异步宽带码分多址（WCDMA）系统中获取码组的方法和装置。 主同步信道搜索单元实现主同步信道时隙定时同步。 然后，次同步信道的1-1搜索单元和1-2搜索单元分别从第一和第二天线接收辅同步信道，开始接收信道的一些时隙和码组候选之间的相关操作，并发送 关于具有超过预定阈值的值的候选的信息给确定单元。 确定单元将接收到的关于候选的信息发送到辅同步信道的第二搜索单元。 次同步信道的第二搜索单元基于所接收的关于候选的信息计算相关特性，并选择具有最高相关特性的码组候选。