公开(公告)号：US06766385B2

公开(公告)日：2004-07-20

申请号：US10041679

申请日：2002-01-07

Applicant: James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

Inventor： James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

IPC: G06F1328

CPC classification number: G06F13/1668 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1072

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract translation: 本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。 该方法包括确定可操作地耦合到存储器件的存储器控​​制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

公开(公告)号：US06725349B2

公开(公告)日：2004-04-20

申请号：US10389092

申请日：2003-03-13

Applicant: Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

Inventor： Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

IPC: G06F1200

CPC classification number: G11C7/1024 ,  G11C7/1021 ,  G11C11/4076 ,  G11C11/4082

Abstract: A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Abstract translation: 提出一种用于优化具有多个存储器组的存储器子系统的基于存储体的控制的方法和装置，所述多个存储器组安装有不同类型的动态随机存取存储器（DRAM）设备。 本发明包括一种改进的DRAM控制器，其包括一组配置寄存器，其存储与主存储器中与DRAM装置填充的每个存储体相对应的配置位。 存储器控制器还包括检测逻辑，其与存储体解码逻辑一起使能存储器控制器确定特定存储体是否填充有页面模式DRAM或扩展数据输出DRAM。 优选实施例还包括列地址选通状态机，其自动控制安装在主存储器中的两种类型的DRAM设备的定时要求，以快速有效地处理访问请求。

公开(公告)号：US06639820B1

公开(公告)日：2003-10-28

申请号：US10186357

申请日：2002-06-27

Applicant: Narendra S. Khandekar ,  James M. Dodd

Inventor： Narendra S. Khandekar ,  James M. Dodd

IPC: G11C506

CPC classification number: G11C5/04 ,  G11C5/00

Abstract: Memory modules, memory systems, and computing devices are described which include memory buffer devices that buffer signals of memory devices. In some embodiments, the memory buffer devices are positioned to reduce the circuit board footprint of the memory buffer devices.

Abstract translation: 描述了存储器模块，存储器系统和计算设备，其包括缓冲存储器件信号的存储器缓冲器件。 在一些实施例中，定位存储器缓冲器件以减少存储器缓冲器件的电路板封装。

公开(公告)号：US06618791B1

公开(公告)日：2003-09-09

申请号：US09677138

申请日：2000-09-29

Applicant: James M. Dodd ,  Michael W. Williams

Inventor： James M. Dodd ,  Michael W. Williams

IPC: G06F1200

CPC classification number: G11C5/143 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.

Abstract translation: 提供了一种用于控制存储器件或其一部分的电源状态的存储器系统和方法。 存储器系统包括诸如DRAM的存储器件，存储器控制器，芯片选择线以及用于检测来自芯片选择线的芯片选择信号的逻辑。 每个存储器件或其中的部分通过芯片选择线连接到存储器控制器。 每个芯片选择线允许将芯片选择信号传输到对应的存储器件或存储器件的相应部分，以选择相应的存储器件或其一部分来接收命令。 提供逻辑来检测芯片选择信号。 当逻辑检测到提供给处于低于其空闲状态的功率状态的相应存储器件或其一部分的芯片选择信号时，存储器件或其一部分自动从较低功率状态移动到 更高的功率状态。

公开(公告)号：US06505282B1

公开(公告)日：2003-01-07

申请号：US08821705

申请日：1997-03-19

Applicant: Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

Inventor： Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

IPC: G06F1200

CPC classification number: G06F12/0684 ,  G06F13/1694

Abstract: In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data out type DRAM module or a page mode type DRAM module, ascertaining the type of DRAM module installed in populated ones of the plurality of memory banks. The DRAM type is determined by storing a predetermined value to a predetermined location in populated ones of the plurality of memory banks, and subsequently reading data from the predetermined location of populated ones of the plurality of memory banks using a page read control signal suitable for the extended data out type DRAM modules. If the data read corresponds to the predetermined value stored, an extended data out type DRAM module is identified.

Abstract translation: 在具有填充到相应的多个动态随机存取存储器（DRAM）模块的多个存储体的存储器子系统中，DRAM模块是扩展数据输出型DRAM模块或页模式型DRAM模块，确定类型 的DRAM模块安装在多个存储体中的填充的存储器中。 DRAM类型通过将预定值存储到多个存储体中的填充的存储体中的预定位置来确定，并且随后使用适合于所述多个存储体的页面读取控制信号从多个存储体中的填充的存储体的预定位置读取数据 扩展数据输出型DRAM模块。 如果数据读取对应于存储的预定值，则识别扩展数据输出型DRAM模块。

公开(公告)号：US06493250B2

公开(公告)日：2002-12-10

申请号：US09753024

申请日：2000-12-28

Applicant: John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

Inventor： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC: G11C506

CPC classification number: G06F13/4256

Abstract: Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

Abstract translation: 公开了使用分支点对点存储器总线架构的存储器系统的方法和装置。 在一个实施例中，主存储器控制器维护与一个存储器模块的点对点总线连接，并且该存储器模块与第二模块维护单独的点到点总线连接。 存储器控制器和第二存储器模块之间的数据通过第一存储器模块上的缓冲电路。 对于从存储器控制器接收到的数据，缓冲电路还将该数据上传到模块总线段到第一组存储器件。 该存储器组存储有第二组存储器件的第二模块总线段。 在缓冲电路和第二组存储器件之间的数据通过在第一存储器件组上通过一个通过电路。 以这种方式，即使当存储器模块包含多于一组的存储器设备时，也可以维持点对点存储器总线体系结构。

公开(公告)号：US06442632B1

公开(公告)日：2002-08-27

申请号：US09662365

申请日：2000-09-13

Applicant: George Hayek ,  Brian Langendorf ,  Aniruddha Kundu ,  Gary Solomon ,  Peter D. MacWilliams ,  James M. Dodd

Inventor： George Hayek ,  Brian Langendorf ,  Aniruddha Kundu ,  Gary Solomon ,  Peter D. MacWilliams ,  James M. Dodd

IPC: G06F1300

CPC classification number: G06F13/4031

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract translation: 公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。 向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

公开(公告)号：US06212589B1

公开(公告)日：2001-04-03

申请号：US08924209

申请日：1997-09-05

Applicant: George Hayek ,  Brian Langendorf ,  Aniruddha Kundu ,  Gary Solomon ,  Peter D. MacWilliams ,  James M. Dodd

Inventor： George Hayek ,  Brian Langendorf ,  Aniruddha Kundu ,  Gary Solomon ,  Peter D. MacWilliams ,  James M. Dodd

IPC: G06F1300

CPC classification number: G06F13/4031

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract translation: 公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。 向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

公开(公告)号：US06148380A

公开(公告)日：2000-11-14

申请号：US735433

申请日：1997-01-02

Applicant: James M. Dodd ,  Richard Malinowski

Inventor： James M. Dodd ,  Richard Malinowski

IPC: G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1631

Abstract: An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.

Abstract translation: 提供了用于提高性能的同步DRAM（syncDRAM）存储器的接口和方法。 通过消除使用推测读取方法在SyncDRAM中打开新页面的数据的步骤，syncDRAM中的读取操作显着加快。 这提供了使用命令生成器在SyncDRAM中打开一页信息以响应数据请求的能力。 还包括推测读取逻辑，以继续从具有无效地址的页面读取，直到发生第二个读取请求。 因此，在发生请求与先前请求相同的页面上的数据的后续读取请求的情况下，可以从该页面上的位置索引和读取数据，而无需首先断言SCS＃和SCAS＃。 这经常删除从读取过程打开页面的步骤，并且随着时间的推移，可以显着加快计算机系统中的整体SyncDRAM读取速度。