公开(公告)号：US06725349B2

公开(公告)日：2004-04-20

申请号：US10389092

申请日：2003-03-13

Applicant: Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

Inventor： Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

IPC: G06F1200

CPC classification number: G11C7/1024 ,  G11C7/1021 ,  G11C11/4076 ,  G11C11/4082

Abstract: A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Abstract translation: 提出一种用于优化具有多个存储器组的存储器子系统的基于存储体的控制的方法和装置，所述多个存储器组安装有不同类型的动态随机存取存储器（DRAM）设备。 本发明包括一种改进的DRAM控制器，其包括一组配置寄存器，其存储与主存储器中与DRAM装置填充的每个存储体相对应的配置位。 存储器控制器还包括检测逻辑，其与存储体解码逻辑一起使能存储器控制器确定特定存储体是否填充有页面模式DRAM或扩展数据输出DRAM。 优选实施例还包括列地址选通状态机，其自动控制安装在主存储器中的两种类型的DRAM设备的定时要求，以快速有效地处理访问请求。

公开(公告)号：US06505282B1

公开(公告)日：2003-01-07

申请号：US08821705

申请日：1997-03-19

Applicant: Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

Inventor： Brian K. Langendorf ,  James M. Dodd ,  Nicholas D. Wade

IPC: G06F1200

CPC classification number: G06F12/0684 ,  G06F13/1694

Abstract: In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data out type DRAM module or a page mode type DRAM module, ascertaining the type of DRAM module installed in populated ones of the plurality of memory banks. The DRAM type is determined by storing a predetermined value to a predetermined location in populated ones of the plurality of memory banks, and subsequently reading data from the predetermined location of populated ones of the plurality of memory banks using a page read control signal suitable for the extended data out type DRAM modules. If the data read corresponds to the predetermined value stored, an extended data out type DRAM module is identified.

Abstract translation: 在具有填充到相应的多个动态随机存取存储器（DRAM）模块的多个存储体的存储器子系统中，DRAM模块是扩展数据输出型DRAM模块或页模式型DRAM模块，确定类型 的DRAM模块安装在多个存储体中的填充的存储器中。 DRAM类型通过将预定值存储到多个存储体中的填充的存储体中的预定位置来确定，并且随后使用适合于所述多个存储体的页面读取控制信号从多个存储体中的填充的存储体的预定位置读取数据 扩展数据输出型DRAM模块。 如果数据读取对应于存储的预定值，则识别扩展数据输出型DRAM模块。

公开(公告)号：US5717873A

公开(公告)日：1998-02-10

申请号：US734730

申请日：1996-10-21

Applicant: Jeffrey L. Rabe ,  Nicholas D. Wade ,  Bruce Young

Inventor： Jeffrey L. Rabe ,  Nicholas D. Wade ,  Bruce Young

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4036

Abstract: Apparatus and a method for eliminating deadlock in a multibus computer system which system includes a primary bus, and a secondary bus, a bridge circuit for joining the primary bus to a bus master, and a second bridge circuit for joining the primary bus to the secondary bus. The invention causes the second bridge circuit to generate a first signal directed to the all bridge circuits to indicate that a bus master on the secondary bus desires access to the secondary bus. All bridge circuits holding data directed to a component on the secondary bus flushes all temporary storage means holding data directed to a component on the secondary bus. The bridge circuits then generate signals to indicate that flushing is complete and the bus master on the secondary bus is granted access to the secondary bus. In one embodiment, the second bridge tests to determine whether the bus master requesting access requires a guaranteed access time and generates a signal to flush temporary storage in the first bridge between memory and the bridge.

Abstract translation: 一种用于消除多总线计算机系统中的死锁的装置和方法，该系统包括主总线和辅助总线，用于将主总线连接到总线主机的桥接电路和用于将主总线连接到次级总线的第二桥接电路 总线。 本发明使得第二桥接电路产生指向全桥电路的第一信号，以指示辅助总线上的总线主机需要访问辅助总线。 保持指向辅助总线上的组件的数据的所有桥接电路刷新所有临时存储装置，其保持指向次级总线上的组件的数据。 然后，桥接电路产生信号以指示冲洗完成，并且次级总线上的总线主机被授予对辅助总线的访问。 在一个实施例中，第二桥接器测试以确定请求访问的总线主机是否需要保证访问时间，并且生成用于冲洗存储器和桥接器之间的第一桥中的临时存储器的信号。

公开(公告)号：US5347648A

公开(公告)日：1994-09-13

申请号：US914777

申请日：1992-07-15

Applicant: Rebecca L. Stamm ,  Ruth I. Bahar ,  Raymond L. Strouble ,  Nicholas D. Wade ,  John H. Edmondson

Inventor： Rebecca L. Stamm ,  Ruth I. Bahar ,  Raymond L. Strouble ,  Nicholas D. Wade ,  John H. Edmondson

IPC: F02B75/02 ,  G06F9/38 ,  G06F12/08 ,  G06F11/00

CPC classification number: G06F9/3836 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F9/3857 ,  F02B2075/025 ,  G06F2212/1032

Abstract: Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that provides limited use of the data in the cache; a read or write request for data not owned in the cache is made to the main memory instead of the cache, even when the data is valid in the cache, although owned data is read from the cache. In ETM, when the processor makes a first write request to data not owned in the cache followed by a second write request to data owned in the cache, write data of the first write request is prevented from being received by the main memory after write data of the second request while permitting writeback of the data owned by the cache. Preferably this is done by sending the write requests from the processor through the non-writeback queue, and when a write request accesses data in a block of data owned by the cache, disowning the block of data in the cache and writing the disowned block of data back to the main memory.

Abstract translation: 来自处理器和高速缓存的回写事务通过写回队列被馈送到主存储器，并且来自处理器和高速缓存的非回写事务通过非回写队列被馈送到主存储器。 当检测到高速缓存错误时，输入错误转换模式（ETM），其提供高速缓存中数据的有限使用; 尽管在高速缓存中读取所有的数据，但是即使数据在高速缓存中有效，对高速缓存中不拥有的数据的读取或写入请求也作为主存储器而不是高速缓存。 在ETM中，当处理器对高速缓存中不拥有的数据进行第一次写入请求，接着对高速缓存中拥有的数据进行第二次写入请求时，在写入数据后，防止第一个写请求的写入数据被主存储器接收 的第二个请求，同时允许回写高速缓存所拥有的数据。 优选地，这是通过从处理器通过非回写队列发送写请求来完成的，并且当写请求访问由高速缓存所拥有的数据块中的数据时，不知道高速缓存中的数据块并写入不存在的块 数据回到主内存。

公开(公告)号：US5818464A

公开(公告)日：1998-10-06

申请号：US960113

申请日：1997-10-27

Applicant: Nicholas D. Wade

Inventor： Nicholas D. Wade

IPC: G06F13/18 ,  G06F15/00

CPC classification number: G06F13/18

Abstract: The shared computer system memory is partitioned between system memory and frame buffer memory. The memory controller and the graphics controller share access to the computer system memory through a single interface bus. An arbitration unit is provided to arbitrate competing usage requests to the memory from the memory controller and the graphics controller. The arbitration unit may form a portion of the memory controller or may be configured as a stand alone unit. In either case, the arbitration unit resolves competing usage requests by applying a prioritization protocol. The arbitration unit grants control of the memory to either the memory controller or the graphics controller depending upon which has asserted a higher priority request. Once the graphics controller has been granted control of the memory, the arbitration unit cannot revoke control from the graphics controller. Rather, the arbitration unit requests that the graphics controller relinquish control. In one embodiment, communication between the arbitration unit and the graphics controller utilizes only two signal lines, a request line and a grant line. A two-wire protocol is disclosed which allows the graphics controller to assert two different levels of priority requests using the single request line. Method and apparatus embodiments of the invention are disclosed.

Abstract translation: 共享计算机系统内存在系统内存和帧缓冲存储器之间进行分区。 存储器控制器和图形控制器通过单个接口总线共享对计算机系统存储器的访问。 提供仲裁单元以从存储器控制器和图形控制器仲裁对存储器的竞争使用请求。 仲裁单元可以形成存储器控制器的一部分，或者可以被配置为独立单元。 在任一情况下，仲裁单元通过应用优先化协议来解决竞争性使用请求。 仲裁单元将存储器的控制权授予存储器控制器或图形控制器，这取决于哪个已经声明了较高的优先级请求。 一旦图形控制器已被授权对存储器的控制，则仲裁单元不能撤销来自图形控制器的控制。 相反，仲裁单元请求图形控制器放弃控制。 在一个实施例中，仲裁单元和图形控制器之间的通信仅使用两条信号线，一条请求线和一条授权线。 公开了一种两线协议，其允许图形控制器使用单个请求线来声明两个不同级别的优先级请求。 公开了本发明的方法和装置实施例。

公开(公告)号：US5625779A

公开(公告)日：1997-04-29

申请号：US366964

申请日：1994-12-30

Applicant: Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

Inventor： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/364 ,  G06F13/4031 ,  G06F13/4036

Abstract: An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

Abstract translation: 耦合在扩展桥和主桥之间的中间总线的仲裁信令机制，用于管理通过中间总线的通信。 主桥包括用于在CPU和扩展桥之间发布事务的CPU发布缓冲器，以及用于存储要写入到DRAM中的数据的DRAM缓冲器。 主桥还包括耦合以从扩展桥接器和耦合到扩展桥的任何其它总线代理接收请求信号的仲裁器。 响应于扩展桥的请求，仲裁器在确认确认信号之前清空CPU发布缓冲区和DRAM缓冲区。 提供了一种被动释放方法，其包括在扩展桥具有总线控制的通信周期期间通过扩展桥信令发送被动释放语义。 主桥可以在再次允许进入扩建桥之前，暂时使用公交车给另一个总线代理。

公开(公告)号：US5404483A

公开(公告)日：1995-04-04

申请号：US902156

申请日：1992-06-22

Applicant: Rebecca L. Stamm ,  Ruth I. Bahar ,  Nicholas D. Wade

Inventor： Rebecca L. Stamm ,  Ruth I. Bahar ,  Nicholas D. Wade

IPC: F02B75/02 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F9/3836 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F9/3857 ,  F02B2075/025 ,  G06F2212/1032

Abstract: A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the cache, saving the specified address in a fill address memory, and sending a fill request to the shared memory. Before return of fill data, the first processor receives a cache coherency request including the specified address from a second processor requesting invalidation of an addressed block of data. The first processor responds by checking whether the fill address memory includes the specified address, and upon finding the specified address in the fill address memory, delaying execution of the cache coherency request until the fill data is returned, and when the fill data is returned, using the fill data without retaining a validated block of the fill data in the cache. In a preferred embodiment, the fill memory is a content-addressable memory including a plurality of entries, and each entry has a fill address, an ownership fill bit (OREAD), an ownership-read invalidate pending bit (OIP), and a read invalidate pending bit (RIP). The OIP or RIP bit is set when execution of a cache coherency request is delayed, and these bits are read upon completion of a fill to execute the delayed request.

Abstract translation: 一种处理器和方法，用于在使用共享存储器的多处理器系统中的优先高速缓冲存储期间延迟高速缓存一致性事务的处理。 第一处理器通过寻址高速缓冲存储器来获取具有指定地址的数据，并且当指定的地址不在高速缓存中时，将指定的地址保存在填充地址存储器中，并且向共享存储器发送填充请求。 在返回填充数据之前，第一处理器从第二处理器接收包括指定地址的高速缓存一致性请求，请求无效地寻址数据块。 第一个处理器通过检查填充地址存储器是否包含指定的地址进行响应，并且在找到填充地址存储器中的指定地址时，延迟高速缓存一致性请求的执行，直到返回填充数据，并且当返回填充数据时， 使用填充数据，而不在缓存中保留填充数据的验证块。 在优选实施例中，填充存储器是包括多个条目的内容寻址存储器，并且每个条目具有填充地址，所有权填充位（OREAD），所有权读取无效等待位（OIP）和读取 使未决位（RIP）无效。 当执行高速缓存一致性请求被延迟时，OIP或RIP位被置位，并且在完成填充时读取这些位以执行延迟的请求。

公开(公告)号：US06574219B1

公开(公告)日：2003-06-03

申请号：US09130399

申请日：1998-08-06

Applicant: Gilbert A. Neiger ,  Nicholas D. Wade ,  Kai Cheng

Inventor： Gilbert A. Neiger ,  Nicholas D. Wade ,  Kai Cheng

IPC: H04J326

CPC classification number: H04L47/10 ,  H04L12/42 ,  H04L47/34

Abstract: In some embodiments, a computer system includes nodes connected through conductors to form a ring. Messages are transmitted on the ring and at least some of the nodes each include control circuitry to receive the messages in a node reception order that is different for each node and order the messages in a global order that is the same for each node having the control circuitry.

Abstract translation: 在一些实施例中，计算机系统包括通过导体连接以形成环的节点。 消息在环上传输，并且至少一些节点每个都包括控制电路，以便以每个节点不同的节点接收顺序接收消息，并且以具有控制的每个节点的全局顺序排序消息 电路。

公开(公告)号：US06393525B1

公开(公告)日：2002-05-21

申请号：US09314233

申请日：1999-05-18

Applicant: Christopher B. Wilkerson ,  Nicholas D. Wade

Inventor： Christopher B. Wilkerson ,  Nicholas D. Wade

IPC: G06F1200

CPC classification number: G06F12/123

Abstract: An LRU with protection method is provided that offers substantial performance benefits over traditional LRU replacement methods by providing solutions to common problems with traditional LRU replacement. By dividing a cache entry list into a filter sublist and a reuse list, population and protection processes can be implemented to reduce associativity and capacity displacement. New cache entries are initially stored in the filter list, and the reuse list is populated with entries promoted from the cache list. Eviction from the filter list and reuse list is done by a protection process that evicts a data entry from the filter, reuse, or global cache list. Many variations of protection and eviction processes are discussed herein, along with the benefits each provides in reducing the effect of unwanted displacement problems present in traditional LRU replacement.

Abstract translation: 提供了一种具有保护方法的LRU，通过为传统LRU更换的常见问题提供解决方案，可提供比传统LRU更换方法更多的性能优势。 通过将缓存条目列表划分为过滤器子列表和重用列表，可以实现人口和保护过程，以降低关联性和容量位移。 新的高速缓存条目最初存储在过滤器列表中，并且重用列表中填充有从缓存列表中提升的条目。 从过滤器列表和重用列表中的排除是通过从过滤器，重用或全局缓存列表中排除数据条目的保护过程完成的。 这里讨论了许多保护和驱逐过程的变化，以及每个在减少传统LRU替换中存在的不期望的位移问题的影响方面提供的益处。

公开(公告)号：US5828854A

公开(公告)日：1998-10-27

申请号：US721271

申请日：1996-09-26

Applicant: Nicholas D. Wade

Inventor： Nicholas D. Wade

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027 ,  G06F13/405

Abstract: An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.

Abstract translation: 公开了一种用于将总线桥连接到多个总线接口的装置和方法。 本发明允许共享总线桥上的输出线，以便利用最小量的专用引脚。 需要快速驱动和接收的总线桥上的信号直接从总线桥连接到总线接口。 无需快速驱动和接收的总线桥上的信号通过缓冲器从总线桥连接到总线接口。 本发明允许总线桥接器连接高速局部总线和多个I / O总线，同时满足每个I / O总线的定时要求。