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公开(公告)号：US20110050326A1
公开(公告)日：2011-03-03
申请号：US12549499
申请日：2009-08-28
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/077
摘要： A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches.
摘要翻译： 电荷泵使用第一开关将第一电容器充电至预定的输入电压。 第一开关耦合到第一电容器的第一端子，用于将第一端子耦合到接收预定输入电压的输入端子。 第二开关将第一电容器的第二端子耦合到参考电压端子。 通过使用第一开关将充电从第一电容器依次传送到输出电容。 使用第三开关和第二电容器将一部分电荷从输出电容顺序地移除到输入端。 配置逻辑提供控制信号以使得多个电荷转移电容器中的一个或多个与所述第一电容器开关相同。
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32.发明申请Built-In Self-Calibration (BISC) Technique for Regulation Circuits Used in Non-Volatile Memory 有权用于非易失性存储器的调节电路的内置自校准（BISC）技术公开(公告)号：US20090243571A1
公开(公告)日：2009-10-01
申请号：US12055538
申请日：2008-03-26
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref′) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage follower circuit (122) which is coupled in feedback to the configurable amplifier (114) for generating an adjusted output voltage at a circuit output (130), where the voltage follow circuit comprises a resistor divider circuit (126) that is controlled by a calibration signal (Cal ) generated by a counter circuit (128) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.
摘要翻译： 提供了参考电压调节电路（143），其中一个或多个输入电压信号（Vref，Vref'）选择性地耦合到可配置放大器（114），可配置放大器（114）通过采样和保持电路（120）耦合到电压跟随器 电路（122），其反馈耦合到可配置放大器（114），用于在电路输出（130）处产生调整的输出电压，其中电压跟随电路包括由校准信号控制的电阻分压器电路（126） 当被配置为响应于时钟信号产生校准信号的比较器时，选择性地耦合到可配置放大器的输出的计数器电路（128）产生的校准电路（Cal
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公开(公告)号：US20090039942A1
公开(公告)日：2009-02-12
申请号：US11835552
申请日：2007-08-08
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.
摘要翻译： 电平转换器包括第一和第二锁存器以及第一至第四晶体管。 第一锁存器具有第一和第二电源端子以及第一和第二节点。 第二锁存器具有第三和第四电源端子，以及第三和第四节点。 第一晶体管具有耦合到第一节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第三节点的第二电流电极和耦合以接收第二偏置电压的控制电极。 第三晶体管具有耦合到第二节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第四晶体管具有耦合到第三晶体管的第二电流电极的第一电流电极，耦合以接收第二偏置电压的控制电极和耦合到第四节点的第二电流电极。
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公开(公告)号：USD366871S
公开(公告)日：1996-02-06
申请号：US10686
申请日：1993-07-14
申请人： Eric Richardson , Jeffrey B. Postupack , Paul W. Brown , Clifford Sielitsky , Peter Phillips , Steven Maker , Lee A. McDavid , Robert Merrill , J. Alan Witmer , William Leathers , Matt P. Bucy , Jeffrey W. Doyle , Michael Geilich , Eric Gottesman , Gerald F. Halstead , Lannelle Jalowiec , Linda J. Donley , Richard Rosenzweig , Troy D. Andrews , Jeffrey C. Cunningham , Alexander Kish , Timothy Pinkham , David Russell , Lisa J. Thompson , Wu-Cheng Tsai , Robert Bristow-Johnson , Tyler Brown , Milton A. Colvin , Cameron W. Jones , Scott C. Peer , Ivor Taylor , Richard Wear , Dave Oren , Mickey Matsumoto
设计人： Eric Richardson , Jeffrey B. Postupack , Paul W. Brown , Clifford Sielitsky , Peter Phillips , Steven Maker , Lee A. McDavid , Robert Merrill , J. Alan Witmer , William Leathers , Matt P. Bucy , Jeffrey W. Doyle , Michael Geilich , Eric Gottesman , Gerald F. Halstead , Lannelle Jalowiec , Linda J. Donley , Richard Rosenzweig , Troy D. Andrews , Jeffrey C. Cunningham , Alexander Kish , Timothy Pinkham , David Russell , Lisa J. Thompson , Wu-Cheng Tsai , Robert Bristow-Johnson , Tyler Brown , Milton A. Colvin , Cameron W. Jones , Scott C. Peer , Ivor Taylor , Richard Wear , Dave Oren , Mickey Matsumoto
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35.发明申请HIGH VOLTAGE FAILURE RECOVERY FOR EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY SYSTEM 有权用于模拟电气可擦除（EEE）存储器系统的高电压故障恢复公开(公告)号：US20160077906A1
公开(公告)日：2016-03-17
申请号：US14484876
申请日：2014-09-12
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0727 , G06F11/073 , G06F11/0751 , G06F11/0787 , G06F11/0793
摘要： The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.
摘要翻译： 本公开提供了用于管理非易失性存储器中的故障扇区的方法和电路。 接收记录地址和读取控制信号，其中记录地址识别非易失性存储器中的位置。 将记录地址与多个死区地址进行比较，其中死扇区地址对应于位于非易失性存储器中的扇区的子集。 响应于记录地址与死区地址之一匹配的第一检测和请求执行读控制信号指示读操作的第二检测的组合，位于记录地址处的数据被确定为无效 非易失性存储器。
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公开(公告)号：US09209810B2
公开(公告)日：2015-12-08
申请号：US14253930
申请日：2014-04-16
IPC分类号： H03L5/00 , H03K19/0185
CPC分类号： H03K19/018528 , H03K19/018521
摘要： An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.
摘要翻译： 在第一电源端子和第二电源端子之间的输出电路接收基于第一电源端子处的电压的第一逻辑状态和基于第一电源端子处的电压的第二逻辑状态之间切换的第一逻辑信号 第二电源端子，并提供与第一逻辑信号互补的第二逻辑信号。 电平转换器处于被配置为在第三电源端子和第四电源端子之间具有第二电压差的第二电源域，其中第二电压差大于第一电压差。 电平转换器的设计使得可以使用具有最短沟道长度和最窄沟道宽度的晶体管的子集来实现。
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37.发明申请Digital Control For Regulation Of Program Voltages For Non-Volatile Memory (NVM) Systems 有权用于非易失性存储器（NVM）系统的程序电压调节的数字控制公开(公告)号：US20150235704A1
公开(公告)日：2015-08-20
申请号：US14185454
申请日：2014-02-20
摘要： Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.
摘要翻译： 公开了用于数字控制以调节非易失性存储器（NVM）系统的编程电压的方法和系统。 所公开的实施例基于与要编程的单元相关联的参数来动态地调节编程电压，以便考虑在编程电压分配线内发生的IR（电流 - 电阻）电压降。 也可以通过这些动态调整来考虑其他电压变化。 要编程的单元的参数可以包括例如要编程的单元的单元地址位置，要编程的单元的数量，和/或与要编程的单元相关联的其它期望的参数。 所公开的实施例使用基于单元参数从查找表获得的数字控制值来调整由用于编程所选择的单元的电压产生电路块产生的输出电压，从而将程序输出电压电平调谐到预定的期望电平。
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公开(公告)号：US09110782B2
公开(公告)日：2015-08-18
申请号：US13457669
申请日：2012-04-27
CPC分类号： G06F12/0246 , G06F2212/1024 , G06F2212/151 , G06F2212/7202 , G06F2212/7203 , G06F2212/7204
摘要： A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.
摘要翻译： 将具有多个模拟电可擦除（EEE）存储器块的非易失性存储器（NVM）的数据传送到EEE的随机存取存储器（RAM）的方法包括访问多个记录，每个记录 块。 如果第一数据信号的数据信号中的任一个是有效的并因此被认为是有效数据信号，则确定。 如果只有一个或者没有一个有效，则有效数据（如果有的话）被加载到RAM中，并且该进程继续进行后续的同时访问。 如果多于一个有效，那么进程停止，直到RAM被加载有效数据，然后该方法继续随后记录的同时访问。
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39.发明授权Sector-based regulation of program voltages for non-volatile memory (NVM) systems 有权基于部门的非易失性存储器（NVM）系统的程序电压调节公开(公告)号：US09013927B1
公开(公告)日：2015-04-21
申请号：US14050962
申请日：2013-10-10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程和正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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40.发明申请SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY (NVM) SYSTEMS 有权针对非易失性存储器（NVM）系统的程序电压的基于行业的规范公开(公告)号：US20150103602A1
公开(公告)日：2015-04-16
申请号：US14050962
申请日：2013-10-10
IPC分类号： G11C16/10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程以及正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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