Systems and methods for code protection in non-volatile memory systems
    1.
    发明授权
    Systems and methods for code protection in non-volatile memory systems 有权
    非易失性存储器系统中代码保护的系统和方法

    公开(公告)号:US09390278B2

    公开(公告)日:2016-07-12

    申请号:US13616922

    申请日:2012-09-14

    IPC分类号: G06F12/14 G06F21/62 G06F21/79

    摘要: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

    摘要翻译: 公开了用于非易失性存储器(NVM)系统中的代码保护的方法和系统。 存储在NVM存储器扇区内的信息(例如引导代码或其他代码块)使用在NVM系统中的程序一次存储区中写入的锁定代码和锁定密钥进行保护。 此外,锁定码可以组合成可以存储在合并保护寄存器中的合并锁定码。 合并的保护寄存器用于控制对受保护的存储器扇区的写访问。 当保护存储器扇区时,锁定代码/密钥对被写入到程序一次区域。 存储锁定代码/密钥对的程序一次区域不能被外部用户读取。 一旦被保护,如果没有锁定代码/密钥对,则无法更新存储器扇区。

    High voltage failure recovery for emulated electrically erasable (EEE) memory system
    2.
    发明授权
    High voltage failure recovery for emulated electrically erasable (EEE) memory system 有权
    用于模拟电可擦除(EEE)存储器系统的高电压故障恢复

    公开(公告)号:US09563491B2

    公开(公告)日:2017-02-07

    申请号:US14484876

    申请日:2014-09-12

    IPC分类号: G06F12/02 G06F11/07

    摘要: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.

    摘要翻译: 本公开提供了用于管理非易失性存储器中的故障扇区的方法和电路。 接收记录地址和读取控制信号,其中记录地址识别非易失性存储器中的位置。 将记录地址与多个死区地址进行比较,其中死扇区地址对应于位于非易失性存储器中的扇区的子集。 响应于记录地址与死区地址之一匹配的第一检测和请求执行读控制信号指示读操作的第二检测的组合,位于记录地址处的数据被确定为无效 非易失性存储器。

    EMULATED ELECTRICALLY ERASABLE MEMORY HAVING SECTOR MANAGEMENT
    3.
    发明申请
    EMULATED ELECTRICALLY ERASABLE MEMORY HAVING SECTOR MANAGEMENT 审中-公开
    具有行业管理功能的模拟电力可擦除存储器

    公开(公告)号:US20130268717A1

    公开(公告)日:2013-10-10

    申请号:US13442028

    申请日:2012-04-09

    IPC分类号: G06F12/00

    摘要: A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid.

    摘要翻译: 半导体存储器件包括易失性存储器和包括多个扇区的非易失性存储器。 多个扇区中的每一个被配置为存储扇区状态指示符和多个数据记录。 控制模块耦合到非易失性存储器和易失性存储器。 控制模块通过扫描扇区来管理扇区,以识别具有无效数据的记录; 当特定扇区中的所有记录无效时,改变特定扇区的状态指示符,并且在特定扇区中的所有记录无效时停止扫描特定扇区。

    EMULATED ELECTRICALLY ERASABLE MEMORY PARALLEL RECORD MANAGEMENT
    4.
    发明申请
    EMULATED ELECTRICALLY ERASABLE MEMORY PARALLEL RECORD MANAGEMENT 有权
    模拟电可擦除记忆并行记录管理

    公开(公告)号:US20130290603A1

    公开(公告)日:2013-10-31

    申请号:US13457669

    申请日:2012-04-27

    IPC分类号: G06F12/00

    摘要: A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.

    摘要翻译: 将具有多个模拟电可擦除(EEE)存储器块的非易失性存储器(NVM)的数据传送到EEE的随机存取存储器(RAM)的方法包括访问多个记录,每个记录 块。 如果第一数据信号的数据信号中的任一个是有效的并因此被认为是有效数据信号,则确定。 如果只有一个或者没有一个有效,则有效数据(如果有的话)被加载到RAM中,并且该进程继续进行后续的同时访问。 如果多于一个有效,那么进程停止,直到RAM被加载有效数据,然后该方法继续随后记录的同时访问。

    Emulated electrically erasable memory parallel record management
    5.
    发明授权
    Emulated electrically erasable memory parallel record management 有权
    模拟电可擦除内存并行记录管理

    公开(公告)号:US09110782B2

    公开(公告)日:2015-08-18

    申请号:US13457669

    申请日:2012-04-27

    IPC分类号: G06F12/00 G06F12/02

    摘要: A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.

    摘要翻译: 将具有多个模拟电可擦除(EEE)存储器块的非易失性存储器(NVM)的数据传送到EEE的随机存取存储器(RAM)的方法包括访问多个记录,每个记录 块。 如果第一数据信号的数据信号中的任一个是有效的并因此被认为是有效数据信号,则确定。 如果只有一个或者没有一个有效,则有效数据(如果有的话)被加载到RAM中,并且该进程继续进行后续的同时访问。 如果多于一个有效,那么进程停止,直到RAM被加载有效数据,然后该方法继续随后记录的同时访问。

    SYSTEMS AND METHODS FOR CODE PROTECTION IN NON-VOLATILE MEMORY SYSTEMS
    6.
    发明申请
    SYSTEMS AND METHODS FOR CODE PROTECTION IN NON-VOLATILE MEMORY SYSTEMS 有权
    非易失性存储器系统中的代码保护系统和方法

    公开(公告)号:US20140082257A1

    公开(公告)日:2014-03-20

    申请号:US13616922

    申请日:2012-09-14

    IPC分类号: G06F12/14 G06F12/02

    摘要: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

    摘要翻译: 公开了用于非易失性存储器(NVM)系统中的代码保护的方法和系统。 存储在NVM存储器扇区内的信息,例如引导代码或其他代码块,使用在NVM系统中的程序一次存储区中写入的锁定代码和锁定键进行保护。 此外,锁定码可以组合成可以存储在合并保护寄存器中的合并锁定码。 合并的保护寄存器用于控制对受保护的存储器扇区的写访问。 当保护存储器扇区时,锁定代码/密钥对被写入到程序一次区域。 存储锁定代码/密钥对的程序一次区域不能被外部用户读取。 一旦被保护,如果没有锁定代码/密钥对,则无法更新存储器扇区。

    Digital control for regulation of program voltages for non-volatile memory (NVM) systems
    7.
    发明授权
    Digital control for regulation of program voltages for non-volatile memory (NVM) systems 有权
    用于调节非易失性存储器(NVM)系统的编程电压的数字控制

    公开(公告)号:US09269442B2

    公开(公告)日:2016-02-23

    申请号:US14185454

    申请日:2014-02-20

    IPC分类号: G11C16/30 G11C16/10 G11C16/08

    摘要: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

    摘要翻译: 公开了用于数字控制以调节非易失性存储器(NVM)系统的编程电压的方法和系统。 所公开的实施例基于与要编程的单元相关联的参数来动态地调节编程电压,以便考虑在编程电压分配线内发生的IR(电流 - 电阻)电压降。 也可以通过这些动态调整来考虑其他电压变化。 要编程的单元的参数可以包括例如要编程的单元的单元地址位置,要编程的单元的数量,和/或与要编程的单元相关联的其它期望的参数。 所公开的实施例使用基于单元参数从查找表获得的数字控制值来调整由用于编程所选择的单元的电压产生电路块产生的输出电压,从而将程序输出电压电平调谐到预定的期望电平。

    Smart charge pump configuration for non-volatile memories
    8.
    发明授权
    Smart charge pump configuration for non-volatile memories 有权
    智能电荷泵配置用于非易失性存储器

    公开(公告)号:US09111629B2

    公开(公告)日:2015-08-18

    申请号:US13441335

    申请日:2012-04-06

    摘要: A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.

    摘要翻译: 半导体存储器件包括非易失性存储器,存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。

    Symmetrical Data Replication For Failure Management In Non-Volatile Memory Systems
    9.
    发明申请
    Symmetrical Data Replication For Failure Management In Non-Volatile Memory Systems 审中-公开
    非易失性存储器系统中的故障管理对称数据复制

    公开(公告)号:US20140258792A1

    公开(公告)日:2014-09-11

    申请号:US13791012

    申请日:2013-03-08

    IPC分类号: G06F12/02 G06F11/00

    摘要: Methods and systems are disclosed for symmetrical replication of data within multiple data subsystems for failure management in non-volatile memory (NVM) systems. Disclosed embodiments perform symmetrical write operations to multiple different data block subsystems so that duplicate subsystems are created. As the subsystems are operated symmetrically, address locations and pointers are the same for each subsystem. If an error is detected in data within one subsystem, the duplicated data at the same symmetrical location within a duplicate subsystem can be used. As such, the endurance and lifetime of NVM systems is greatly enhanced. These extended lifetime NVM systems can then be used, for example, to emulate EEPROM (erasable programmable read only memory) systems.

    摘要翻译: 公开了用于在用于非易失性存储器(NVM)系统中的故障管理的多个数据子系统内的数据的对称复制的方法和系统。 公开的实施例对多个不同的数据块子系统执行对称的写入操作,从而创建重复的子系统。 由于子系统对称运行,每个子系统的地址位置和指针是相同的。 如果在一个子系统内的数据中检测到错误,则可以使用重复子系统内相同对称位置处的复制数据。 因此,NVM系统的耐用性和使用寿命大大提高。 这些延长使用寿命的NVM系统可用于例如仿真EEPROM(可擦除可编程只读存储器)系统。

    Adaptive error correction for non-volatile memories
    10.
    发明授权
    Adaptive error correction for non-volatile memories 有权
    非易失性存储器的自适应纠错

    公开(公告)号:US08793558B2

    公开(公告)日:2014-07-29

    申请号:US13595282

    申请日:2012-08-27

    IPC分类号: H03M13/00

    摘要: Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.

    摘要翻译: 公开了用于非易失性存储器的自适应纠错,其动态地调整读出放大器读取检测窗口。 存储器控制电路使用纠错码(ECC)例程来检测使用这些ECC例程不可校正的位错误。 存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。 校正的数据可以输出到外部电路。 当随后的读取操作尝试访问先前遭受比特故障的地址位置时,也可以存储校正的数据以供稍后访问。 相对于不是非易失性存储器的存储器也可以使用自适应纠错。