公开(公告)号：US07708460B1

公开(公告)日：2010-05-04

申请号：US11904843

申请日：2007-09-28

申请人： Jeffrey T. Watt ,  Shuxian Chen

发明人： Jeffrey T. Watt ,  Shuxian Chen

IPC分类号： G01K1/00

CPC分类号： G01K7/01

摘要： A method for measuring temperature on a silicon device includes activating a heat source on the silicon device. A value of a parameter of an electronic component on the silicon device is measured. A temperature associated with the electronic component is determined from the value of the parameter.

摘要翻译： 用于测量硅器件上的温度的方法包括激活硅器件上的热源。 测量硅器件上的电子部件的参数的值。 与电子元件相关联的温度由参数的值确定。

公开(公告)号：US07639474B1

公开(公告)日：2009-12-29

申请号：US12336182

申请日：2008-12-16

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01G4/228

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01G4/38 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

摘要翻译： 多段并联线电容器包括在半导体衬底上制造的基本相同的多个电容器段。 每个段包括形成在衬底上方的第一金属层中的至少第一和第二交错金属指，以及形成在第二金属层中的第三和第四交错金属指。 第一组和第四组连接在一起以形成电容器的一个板，并且第二组和第三组连接以形成第二板。 多个电容器段被布置成具有M行和N列的矩阵。 多个电容器段以使得矩阵的每列中的电容器段并联连接的方式相互连接。 第一和第二金属线选择性地连接第一行和最后一行中的不同电容器段的板，并且用作多段并联线电容器的两个相对的端子。

公开(公告)号：US07511932B1

公开(公告)日：2009-03-31

申请号：US11836700

申请日：2007-08-09

申请人： Antonio Gallerano ,  Jeffrey T. Watt ,  Srinivas Perisetty ,  Cheng-Hsiung Huang

发明人： Antonio Gallerano ,  Jeffrey T. Watt ,  Srinivas Perisetty ,  Cheng-Hsiung Huang

IPC分类号： H02H9/00 ,  H02H1/00

CPC分类号： H01L27/0266

摘要： The present invention is an ESD protection circuit that discharges both positive and negative electrostatic events. A preferred embodiment of the circuit comprises a first NMOS transistor having a source and drain connected between ground and an I/O pad and second and third NMOS transistors and a resistor connected in series between ground and the I/O pad. The gate and body of the first transistor and the bodies of the second and third transistors are connected to a node between the second and third transistors; the gate of the second transistor is connected to the I/O pad through a second resistor; and the gate of the third transistor is connected to ground. The second and third transistors maintain the gate and body voltage of the first transistor at the pad voltage when the pad experiences negative voltages and at ground voltage when the pad experiences positive voltages. As a result, the first transistor can discharge both negative and positive ESC events through parasitic bipolar conduction, without any additional circuits such as diodes used either to stop leakage currents or to conduct ESD current.

摘要翻译： 本发明是放电正静电事件和负静电事件两者的ESD保护电路。 电路的优选实施例包括第一NMOS晶体管，其源极和漏极连接在地与I / O焊盘之间，第二和第三NMOS晶体管和电阻串联连接在地和I / O焊盘之间。 第一晶体管的栅极和主体以及第二和第三晶体管的主体连接到第二和第三晶体管之间的节点; 第二晶体管的栅极通过第二电阻器连接到I / O焊盘; 并且第三晶体管的栅极连接到地。 当焊盘经受负电压时，第二晶体管和第三晶体管的栅极和体电压保持在焊盘电压，并且当焊盘经受正电压时，其保持接地电压。 因此，第一晶体管可以通过寄生双极导通来放电负和正的ESC事件，而不需要任何额外的电路，例如用于阻止漏电流或导通ESD电流的二极管。

公开(公告)号：US07321236B2

公开(公告)日：2008-01-22

申请号：US11672444

申请日：2007-02-07

申请人： Irfan Rahim ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： H03K17/16

CPC分类号： H03K19/0027 ,  H03K2217/0018

摘要： Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

摘要翻译： 公开了用于改善可编程逻辑器件（PLD）的性能的装置和方法。 PLD包括被配置为分别向传输晶体管的栅极和传输晶体管的主体提供一对电压的存储单元。

公开(公告)号：US06492710B1

公开(公告)日：2002-12-10

申请号：US09877905

申请日：2001-06-07

申请人： Jeffrey T. Watt

发明人： Jeffrey T. Watt

IPC分类号： H01L2176

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493

摘要： A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

摘要翻译： 提供了一种用于将电路与相同导电类型的衬底良好隔离的装置和方法。 特别地，提供了一种集成电路，其包括布置在半导体衬底上的电路，其中没有布置在阱和衬底之间的相反导电类型的层。 集成电路还可以包括沿着电路阱的相对侧边界延伸的一对隔离阱。 隔离阱和电路阱可以被调整为使得在衬底和一对隔离阱之间施加隔离电压时可以形成电路阱下面的单个连续耗尽区。 这种耗尽区域的形成可以有利地将电路与下面的衬底良好隔离。

公开(公告)号：US08946001B1

公开(公告)日：2015-02-03

申请号：US13349531

申请日：2012-01-12

申请人： Jeffrey T. Watt ,  Antonio Gallerano

发明人： Jeffrey T. Watt ,  Antonio Gallerano

IPC分类号： H01L21/332

CPC分类号： H01L27/0277

摘要： An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.

摘要翻译： 静电放电（ESD）保护电路包括：第一晶体管阵列，其具有掺杂有第一类型材料的源极和漏极，并排布置在第一块中;以及第二晶体管阵列，其具有源极和漏极掺杂有第一 材料类型，平行布置在第二块中。 ESD保护电路还包括掺杂有与第一类型材料互补的第二类型材料的第一和第二晶体阵列之间的有源区。

公开(公告)号：US08289755B1

公开(公告)日：2012-10-16

申请号：US12571346

申请日：2009-09-30

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

摘要翻译： 提供了显示对软错误扰乱的抗扰度的内存元素。 存储器元件可以具有交叉耦合的反相器。 可以使用可编程施密特触发器来实现逆变器。 存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。 存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。 写使能晶体管可以桥接四个节点中的两个。 存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。 当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。 当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。

公开(公告)号：US08089744B1

公开(公告)日：2012-01-03

申请号：US11211060

申请日：2005-08-24

申请人： Irfan Rahim ,  Cheng Hsiung Huang ,  Yow-Juang Bill Liu ,  Jeffrey T. Watt ,  Hugh Sung-Ki O

发明人： Irfan Rahim ,  Cheng Hsiung Huang ,  Yow-Juang Bill Liu ,  Jeffrey T. Watt ,  Hugh Sung-Ki O

IPC分类号： H02H3/22

CPC分类号： H01L27/0277

摘要： An integrated circuit (IC) includes a multiple-finger transistor structure. The multiple-finger transistor structure includes one transistor configured as a ballasted device. The multiple-finger transistor structure further includes a second transistor configured as a trigger device for the ballasted device.

摘要翻译： 集成电路（IC）包括多指晶体管结构。 多指晶体管结构包括被配置为镇流器件的一个晶体管。 多指晶体管结构还包括被配置为用于镇流器件的触发器件的第二晶体管。

公开(公告)号：US20110221560A1

公开(公告)日：2011-09-15

申请号：US12721402

申请日：2010-03-10

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F2017/0046 ,  H01F2017/0086

摘要： An integrated circuit inductor may have upper and lower loop-shaped line portions that are connected in series. The upper and lower portions may have 45° bends that form hexagonal or octagonal loops. Each loop portion may have one or more turns. Intervening metal-free regions of metal routing layers may be formed between the two layers to reduce capacitive coupling. Each loop portion may have sets of two or more metal lines shorted in parallel by vias. The upper and lower loops may be laterally offset or nested to reduce capacitive coupling.

摘要翻译： 集成电路电感器可以具有串联连接的上下环形线部分。 上部和下部可以具有形成六边形或八边形环的45°弯曲。 每个环路部分可以具有一个或多个匝数。 可以在两个层之间形成金属布线层的不间断的金属区域，以减少电容耦合。 每个环部分可以具有由通孔平行短路的两条或更多条金属线组。 上下环可以侧向偏移或嵌套以减小电容耦合。

公开(公告)号：US07990664B1

公开(公告)日：2011-08-02

申请号：US11639792

申请日：2006-12-14

申请人： Srinivas Perisetty ,  Antonio Gallerano ,  Jeffrey T. Watt ,  Cheng-Hsiung Huang

发明人： Srinivas Perisetty ,  Antonio Gallerano ,  Jeffrey T. Watt ,  Cheng-Hsiung Huang

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0277

摘要： An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.

摘要翻译： ESD保护电路以分布式的方式集成到FPGA的核心中，将一个或多个晶体管的主体耦合到FPGA的电源引脚和/或接地引脚。 ESD保护电路包括一个或多个正放电路径和一个或多个负排出路径。 在正的ESD事件的情况下，正的放电路径导通，负的放电路径关闭。 在负ESD事件的情况下，正的放电路径关闭，负的放电路径导通。 在任一情况下，晶体管的主体跟踪电源引脚和/或接地引脚上的电压，以保护芯不被静电放电损坏。