Abstract:
The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.
Abstract:
A method an apparatus to dynamically modify the internal compensation of a low drop-out (LDO) linear voltage regulator is presented. The process involves creating an additional equivalent series resistance (ESR) from an internal circuit. The additional ESR of the internal circuit is sufficient to ensure DC output stability. This allows the ESR of the output capacitance to be reduced to zero if desired, for improved transient response. The zero induced by the ESR of the internal circuit is frequency compensated, so that it tracks the position of the output pole as the load varies.
Abstract:
A wall control interface for power management includes a transmitting circuit that generates a switching signal to control a switch and achieve a phase modulation to a power line signal in response to a transmitting-data. A receiving circuit is coupled to detect the phase of the power line signal for generating a data signal and a receiving-data in response to the phase of the power line signal. The receiving circuit further generates a control signal to control power of a load in accordance with the data signal or the receiving-data. The phase modulation is achieved by controlling a turn-on angle of the power line signal. The switch remains in a turn-on state during the normal condition, which achieves good power and low current harmonic. The phase modulation is only performed during the communication of the power management.
Abstract:
A switching regulator of a power converter is provided and includes a feedback-input circuit, a programming circuit, and a peak-current-threshold circuit. The feedback-input circuit is coupled to a terminal of the switching regulator for receiving a feedback signal. The feedback-input circuit is operated in a first range of a terminal signal. The programming circuit is coupled to the terminal for generating a programming signal. The programming signal is operated in a second range of the feedback signal. The peak-current-threshold circuit generates a threshold signal in accordance with the programming signal. The feedback signal is coupled to regulate the output of the power converter, and the threshold signal is coupled to limit a peak switching current of the power converter.
Abstract:
A switching controller for parallel power converters is disclosed. The switching controller includes an input circuit coupled to an input terminal of the switching controller to receive an input signal. An integration circuit is coupled to the input circuit to generate an integration signal in response to the pulse width of the input signal. A control circuit generates a switching signal for switching the power converters. The switching signal is enabled in response to the enabling of the input signal. A programmable delay time is generated between the input signal and the switching signal. The pulse width of the switching signal is determined in response to the integration signal.
Abstract:
An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.
Abstract:
The present invention discloses a switching control circuit for a primary-side controlled power converter. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge time. A time constant of the integrator is correlated with the switching frequency, thus the current-feedback signal is proportional to an output current of the power converter. A PWM circuit controls the pulse width of the switching signal in response to the outputs of a voltage-loop error amplifier and a current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.
Abstract:
The invention presents a switching control circuit for a primary-side-controlled power converter. A pattern generator produces a digital pattern to control a programmable capacitor that is connected to an oscillator, which produces frequency hopping to reduce the EMI. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal by multi-sampling a voltage signal of a transformer. A current-waveform detector and an integrator generate a feedback signal. The integration of a current-waveform signal with a timing signal generates the average-current signal. Time constant of the integrator is correlated to the switching frequency. The oscillator generates the timing signal and a pulse signal in response to the output of a current-loop error amplifier. A PWM circuit generates the switching signal in response to the pulse signal and the output of a voltage-loop error amplifier for switching the switching device and regulating the output of the power converter.
Abstract:
An electrostatic discharge (ESD) device, which functions like a diode during normal IC operation and like a SCR during an electrostatic discharge event, is provided. To form an equivalent SCR structure, the ESD device includes a plurality of N+ regions and a plurality of P+ regions formed inside an N-well. The P+ regions and the N+ regions are formed adjacent to each other in a sequence, and the regions located at both ends of the sequence are the N+ regions. In addition, the ESD device is integrated with a pad and is formed under the pad. Furthermore, since the pad has a large surface area and is plated to be a good electrical conductor, the current distribution in the ESD device is uniform.
Abstract:
The present invention provides a primary-side flyback power converter that supplies a constant voltage output and a constant current output. To generate a well-regulated output voltage under varying load conditions, a PWM controller is included in the power converter in order to generate a PWM signal controlling a switching transistor in response to a flyback voltage sampled from a first primary winding of the power supply transformer. Several improvements are included in this present invention to overcome the disadvantages of prior-art flyback power converters. Firstly, the flyback energy of the first primary winding is used as a DC power source for the PWM controller in order to reduce power consumption. A double sample amplifier samples the flyback voltage just before the transformer current drops to zero. Moreover, an offset current is pulled from a detection input of the double sample amplifier in order to generate a more accurate DC output voltage. The offset current is generated in response to the temperature in order to compensate for temperature-induced voltage fluctuations across the output rectifier. Ultimately, in order to maintain a constant output current, the PWM controller modulates the switching frequency in response to the output voltage.