公开(公告)号：US20130009207A1

公开(公告)日：2013-01-10

申请号：US13614072

申请日：2012-09-13

Applicant: John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

Inventor： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC: H01L29/74

CPC classification number: H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract translation: 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

公开(公告)号：US20120300349A1

公开(公告)日：2012-11-29

申请号：US13115492

申请日：2011-05-25

Applicant: Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

Inventor： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

IPC: H02H9/00 ,  G06F17/50

CPC classification number: H02H9/046 ,  G06F17/5063 ,  H01L27/0285

Abstract: Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.

Abstract translation: 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

公开(公告)号：US20120176721A1

公开(公告)日：2012-07-12

申请号：US12987276

申请日：2011-01-10

Applicant: Robert J. GAUTHIER, JR. ,  Junjun LI ,  Souvick MITRA

Inventor： Robert J. GAUTHIER, JR. ,  Junjun LI ,  Souvick MITRA

IPC: H05F3/02

CPC classification number: H01L27/0285

Abstract: Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.

Abstract translation: 提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/​​输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。 第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。 第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

公开(公告)号：US08138546B2

公开(公告)日：2012-03-20

申请号：US12127946

申请日：2008-05-28

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20120004896A1

公开(公告)日：2012-01-05

申请号：US12826958

申请日：2010-06-30

Applicant: Junjun Li ,  Rahul Nayak

Inventor： Junjun Li ,  Rahul Nayak

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5068

Abstract: A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.

Abstract translation: 提供了行为模型，其被配置为模拟除了组件的组件模型之外的组件的行为的一个方面。 行为模型可以包含在用于模拟电路运行的电路模型中。 电路模型可以包括组件的组件模型和与组件模型并联或串联的对应行为模型。 组件模型和行为模型可以共同模拟电路中组件的所有行为。 在一个实施例中，行为模型模拟组件所呈现的回弹行为。

公开(公告)号：US20110185332A1

公开(公告)日：2011-07-28

申请号：US12695494

申请日：2010-01-28

Applicant: Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

Inventor： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

Abstract translation: 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US20100265622A1

公开(公告)日：2010-10-21

申请号：US12424169

申请日：2009-04-15

Applicant: John B. CAMPI, JR. ,  Shunhua T. CHANG ,  Kiran V. CHATTY ,  Robert J. GAUTHIER, JR. ,  Junjun LI ,  Mujahid MUHAMMAD

Inventor： John B. CAMPI, JR. ,  Shunhua T. CHANG ,  Kiran V. CHATTY ,  Robert J. GAUTHIER, JR. ,  Junjun LI ,  Mujahid MUHAMMAD

IPC: H02H9/04 ,  H01L27/06

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.

Abstract translation: 公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。 电路包括在ESD事件期间关闭层叠的NFET静电放电（ESD）保护电路的顶部NFET的中间接点控制电路。

公开(公告)号：US07786535B2

公开(公告)日：2010-08-31

申请号：US12059034

申请日：2008-03-31

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC: H01L29/78

CPC classification number: H01L27/1203

Abstract: Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

Abstract translation: 高压集成电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。 第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将第一和第二栅极电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

公开(公告)号：US07782580B2

公开(公告)日：2010-08-24

申请号：US11865820

申请日：2007-10-02

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H02H9/00

CPC classification number: H01L27/0285

Abstract: An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract translation: 一种用于保护集成电路芯片免受ESD事件的电子放电（ESD）保护电路。 ESD保护电路包括一叠BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及响应于ESD事件触发BigFET栅极驱动器来驱动BigFET的栅极。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

公开(公告)号：US20090310267A1

公开(公告)日：2009-12-17

申请号：US12140485

申请日：2008-06-17

Applicant: Robert J. Gauthier, JR. ,  Junjun Li ,  Ankit Srivastava

Inventor： Robert J. Gauthier, JR. ,  Junjun Li ,  Ankit Srivastava

IPC: H02H9/00

CPC classification number: H03F3/45188 ,  H01L27/0251 ,  H03F1/52 ,  H03F1/523 ,  H03F2203/45466 ,  H03F2203/45486 ,  H03F2203/45504

Abstract: A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.

Abstract translation: 在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。