公开(公告)号：US09041825B2

公开(公告)日：2015-05-26

申请号：US13609844

申请日：2012-09-11

Applicant: Kenji Numata

Inventor： Kenji Numata

IPC: H04N5/225 ,  H04N1/21 ,  H04N5/232

CPC classification number: H04N5/23232 ,  H04N5/23209 ,  H04N2005/2255

Abstract: An image processing apparatus of the present invention includes: a video input section to which live video obtained by picking up an image of an object is inputted; a frame interpolation processing section which, by inserting an interpolated image between images of frames constituting the live video, performs processing for generating and outputting interpolated video of a frame rate set in advance; and a control section which, when an instruction for freezing video displayed on a display section is made, operates so as to cause a still image of a frame constituting the live video to be displayed on the display section.

Abstract translation: 本发明的图像处理装置包括：输入通过拍摄对象的图像而获得的实况视频的视频输入部; 帧内插处理部，通过在构成实时视频的帧的图像之间插入内插图像，执行用于生成并输出预先设定的帧速率的内插视频的处理; 以及控制部分，当进行用于冻结显示在显示部分上的视频的指令时，操作以使得构成实时视频的帧的静止图像显示在显示部分上。

公开(公告)号：US20120209064A1

公开(公告)日：2012-08-16

申请号：US13368744

申请日：2012-02-08

Applicant: Kenji NUMATA

Inventor： Kenji NUMATA

IPC: A61B1/04

CPC classification number: A61B1/00057 ,  A61B1/05

Abstract: An endoscope apparatus 1 includes a main body 4 to which a scope having an image pickup device at a distal end portion 8 of an insertion portion 7b is detachably attachable, a video signal processing section 22, a display section 5 and a control section 21. The control section 21 displays on the display section 5 a message for instructing a user to light-shield the distal end portion 8 according to an instruction for starting initialization processing to acquire a reference image of the image pickup device, acquires the reference image with the distal end portion 8 light-shielded and stores the acquired reference image in a memory 27.

Abstract translation: 内窥镜装置1包括：主体4，具有可拆卸地安装在插入部7b的前端部8的具有图像拾取装置的镜头，视频信号处理部22，显示部5和控制部21。 控制部分21在显示部分5上显示用于指示用户根据用于开始初始化处理的指令来屏蔽远端部分8的消息以获取图像拾取装置的参考图像的消息，获取参考图像 远端部分8屏蔽并将获取的参考图像存储在存储器27中。

公开(公告)号：US5862090A

公开(公告)日：1999-01-19

申请号：US959466

申请日：1997-10-28

Applicant: Kenji Numata ,  Syuso Fujii

Inventor： Kenji Numata ,  Syuso Fujii

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

Abstract translation: 半导体存储器件包括具有分组为多个单元块并以矩阵形式布置的多个存储单元的单元阵列，多个字线，多个位线，位线读出放大器（S / A）， 单元块选择电路，多个数据I / O线，行解码器，多个列选择信号线，列解码器和数据缓冲电路。 数据缓冲电路包括连接到数据I / O线的第一预充电电路，用于将数据I / O线预充电到与位线的预充电电位相同的电位;第二预充电电路，连接到数据I / O线，用于将数据I / O线预充电到与位线的预充电电位不同的电位，以及用于产生要提供给第一和第二预充电电路的控制信号的选择驱动电路，以及选择性地驱动第一和 第二预充电电路，用于基于控制信号感测读出到数据I / O线的数据。

公开(公告)号：US5640351A

公开(公告)日：1997-06-17

申请号：US601859

申请日：1996-02-15

Applicant: Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

Inventor： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC classification number: G11C11/4096 ,  G11C7/10

Abstract: According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

Abstract translation: 根据本发明，通过选择列来形成多个存储单元阵列共用的数据总线，以防止发生数据冲突。 具体地说，两个存储单元阵列共有数据总线。 列解码器被提供有控制信号以控制列选择逻辑电路。 列选择逻辑电路被如此控制，以便在同时访问两个单元阵列期间防止响应于控制信号读出到数据总线的数据彼此相冲突。

公开(公告)号：US5594265A

公开(公告)日：1997-01-14

申请号：US799342

申请日：1991-11-27

Applicant: Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

Inventor： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0251

Abstract: According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

Abstract translation: 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。