公开(公告)号：US5734619A

公开(公告)日：1998-03-31

申请号：US944729

申请日：1992-09-15

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

公开(公告)号：US5970006A

公开(公告)日：1999-10-19

申请号：US182892

申请日：1998-10-30

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit,a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

摘要翻译： 半导体存储器件包括具有分组为多个单元块并以矩阵形式布置的多个存储单元的单元阵列，多个字线，多个位线，位线读出放大器（S / A）， 单元块选择电路，多个数据I / O线，行解码器，多个列选择信号线，列解码器和数据缓冲电路。 数据缓冲电路包括连接到数据I / O线的第一预充电电路，用于将数据I / O线预充电到与位线的预充电电位相同的电位;第二预充电电路，连接到数据I / O线，用于将数据I / O线预充电到与位线的预充电电位不同的电位，以及用于产生要提供给第一和第二预充电电路的控制信号的选择驱动电路，以及选择性地驱动第一和 第二预充电电路，用于基于控制信号感测读出到数据I / O线的数据。

公开(公告)号：US5949109A

公开(公告)日：1999-09-07

申请号：US790804

申请日：1997-01-30

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

摘要翻译： 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

公开(公告)号：US5862090A

公开(公告)日：1999-01-19

申请号：US959466

申请日：1997-10-28

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

摘要翻译： 半导体存储器件包括具有分组为多个单元块并以矩阵形式布置的多个存储单元的单元阵列，多个字线，多个位线，位线读出放大器（S / A）， 单元块选择电路，多个数据I / O线，行解码器，多个列选择信号线，列解码器和数据缓冲电路。 数据缓冲电路包括连接到数据I / O线的第一预充电电路，用于将数据I / O线预充电到与位线的预充电电位相同的电位;第二预充电电路，连接到数据I / O线，用于将数据I / O线预充电到与位线的预充电电位不同的电位，以及用于产生要提供给第一和第二预充电电路的控制信号的选择驱动电路，以及选择性地驱动第一和 第二预充电电路，用于基于控制信号感测读出到数据I / O线的数据。

公开(公告)号：US5594265A

公开(公告)日：1997-01-14

申请号：US799342

申请日：1991-11-27

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

摘要翻译： 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

公开(公告)号：US5233558A

公开(公告)日：1993-08-03

申请号：US805965

申请日：1991-12-12

申请人： Syuso Fujii ,  Takeshi Nagai

发明人： Syuso Fujii ,  Takeshi Nagai

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/417

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/1006

摘要： Memory cell arrays containing dynamic memory cells and write/read circuits for these memory cell arrays are arranged alternately. In the write/read circuit, read amplifiers are provided at a rate of one for every four columns (bit line pairs). This read amplifier is composed of a preamplifier and a main amplifier. Each column is provided with a multiplexer, which selects a column and connects it to the preamplifier of a read amplifier. The signal amplified by this preamplifier is supplied to the main amplifier. The current-mirror load circuit of this main amplifier is in common use by a plurality of read amplifiers.

公开(公告)号：US5019729A

公开(公告)日：1991-05-28

申请号：US382493

申请日：1989-07-21

申请人： Tohru Kimura ,  Syuso Fujii ,  Takashi Ohsawa

发明人： Tohru Kimura ,  Syuso Fujii ,  Takashi Ohsawa

IPC分类号： G11C11/409 ,  H03K19/0185

CPC分类号： H03K19/018528 ,  H03K19/01855

摘要： A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.

摘要翻译： 缓冲电路包括第一和第二差分放大型缓冲电路。 第一和第二差分放大型缓冲电路的输入节点连接在一起，并且第一和第二差分放大型缓冲电路的输出节点也彼此连接。 第一差分放大型缓冲电路由作为P沟道MOS晶体管的负载的一对驱动P沟道MOS晶体管和N沟道MOS晶体管构成，并连接构成电流镜电路。 第二差分放大型缓冲电路由作为负载的P沟道MOS晶体管构成，并连接构成电流镜电路和一对驱动N沟道MOS晶体管。

公开(公告)号：US4994874A

公开(公告)日：1991-02-19

申请号：US425950

申请日：1989-10-24

申请人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

发明人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02

CPC分类号： H01L27/0259

摘要： First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.

摘要翻译： 在N型半导体衬底中形成的P型半导体衬底或P阱区域的表面区域中，第一至第三N +型杂质区彼此分开地预定距离地形成。 第一杂质区域连接到电源，第二杂质区域连接到接地端子。 形成在第一和第二杂质区域之间的第三杂质区域连接到另一端连接到信号输入焊盘的输入保护电阻器的一端。 位于第一和第三杂质区域之间的第一杂质区域，第三杂质区域和P型半导体衬底或P阱区域的部分构成用于输入保护的第一双极晶体管，第二杂质区域，第三杂质区域 位于第二和第三杂质区之间的P型半导体衬底或P阱区的部分构成用于输入保护的第二双极晶体管。 电阻器和第一和第二双极晶体管构成输入保护电路。

公开(公告)号：US4941031A

公开(公告)日：1990-07-10

申请号：US416604

申请日：1989-10-03

申请人： Jumpei Kumagai ,  Syuso Fujii

发明人： Jumpei Kumagai ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/0207 ,  G11C11/4097 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922

摘要： A signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal at about 1/2C.sub.F.

公开(公告)号：US4931992A

公开(公告)日：1990-06-05

申请号：US310020

申请日：1989-02-09

申请人： Masaki Ogihara ,  Yoshio Okada ,  Syuso Fujii

发明人： Masaki Ogihara ,  Yoshio Okada ,  Syuso Fujii

IPC分类号： G11C11/4094

CPC分类号： G11C11/4094

摘要： A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.

摘要翻译： 半导体存储器包括用于存储数据的存储单元，用于传送数据的位线对，用于放大来自位线对的数据的读出放大器，直接连接到位线对的恢复电路，用于恢复半导体中的数据 存储器和连接在恢复电路和读出放大器之间的一对恒定电压势垒晶体管，用于增加感测速度。