公开(公告)号：US5594265A

公开(公告)日：1997-01-14

申请号：US799342

申请日：1991-11-27

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

摘要翻译： 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

公开(公告)号：US5949109A

公开(公告)日：1999-09-07

申请号：US790804

申请日：1997-01-30

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

摘要翻译： 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

公开(公告)号：US5862090A

公开(公告)日：1999-01-19

申请号：US959466

申请日：1997-10-28

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

摘要翻译： 半导体存储器件包括具有分组为多个单元块并以矩阵形式布置的多个存储单元的单元阵列，多个字线，多个位线，位线读出放大器（S / A）， 单元块选择电路，多个数据I / O线，行解码器，多个列选择信号线，列解码器和数据缓冲电路。 数据缓冲电路包括连接到数据I / O线的第一预充电电路，用于将数据I / O线预充电到与位线的预充电电位相同的电位;第二预充电电路，连接到数据I / O线，用于将数据I / O线预充电到与位线的预充电电位不同的电位，以及用于产生要提供给第一和第二预充电电路的控制信号的选择驱动电路，以及选择性地驱动第一和 第二预充电电路，用于基于控制信号感测读出到数据I / O线的数据。

公开(公告)号：US5734619A

公开(公告)日：1998-03-31

申请号：US944729

申请日：1992-09-15

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

公开(公告)号：US5970006A

公开(公告)日：1999-10-19

申请号：US182892

申请日：1998-10-30

申请人： Kenji Numata ,  Syuso Fujii

发明人： Kenji Numata ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

摘要： A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit,a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

摘要翻译： 半导体存储器件包括具有分组为多个单元块并以矩阵形式布置的多个存储单元的单元阵列，多个字线，多个位线，位线读出放大器（S / A）， 单元块选择电路，多个数据I / O线，行解码器，多个列选择信号线，列解码器和数据缓冲电路。 数据缓冲电路包括连接到数据I / O线的第一预充电电路，用于将数据I / O线预充电到与位线的预充电电位相同的电位;第二预充电电路，连接到数据I / O线，用于将数据I / O线预充电到与位线的预充电电位不同的电位，以及用于产生要提供给第一和第二预充电电路的控制信号的选择驱动电路，以及选择性地驱动第一和 第二预充电电路，用于基于控制信号感测读出到数据I / O线的数据。

公开(公告)号：US06295241B1

公开(公告)日：2001-09-25

申请号：US08251649

申请日：1994-05-31

申请人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

发明人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

IPC分类号： G11C702

CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4099

摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

摘要翻译： 这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。 位线包括一对位线。 存储器单元耦合到字线和位线对的一个位线。 存储单元由亚微米尺寸的MOSFET组成。 读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。 放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。 它具有由双极晶体管组成的驱动器部分。

公开(公告)号：US5532963A

公开(公告)日：1996-07-02

申请号：US523741

申请日：1995-09-05

申请人： Natsuki Kushiyama ,  Tohru Furuyama ,  Kenji Numata

发明人： Natsuki Kushiyama ,  Tohru Furuyama ,  Kenji Numata

IPC分类号： G11C29/02 ,  G11C29/24 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

摘要翻译： 半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟 通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线， 线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据 的存储单元阵列到相关位线上。

公开(公告)号：US09041825B2

公开(公告)日：2015-05-26

申请号：US13609844

申请日：2012-09-11

申请人： Kenji Numata

发明人： Kenji Numata

IPC分类号： H04N5/225 ,  H04N1/21 ,  H04N5/232

CPC分类号： H04N5/23232 ,  H04N5/23209 ,  H04N2005/2255

摘要： An image processing apparatus of the present invention includes: a video input section to which live video obtained by picking up an image of an object is inputted; a frame interpolation processing section which, by inserting an interpolated image between images of frames constituting the live video, performs processing for generating and outputting interpolated video of a frame rate set in advance; and a control section which, when an instruction for freezing video displayed on a display section is made, operates so as to cause a still image of a frame constituting the live video to be displayed on the display section.

摘要翻译： 本发明的图像处理装置包括：输入通过拍摄对象的图像而获得的实况视频的视频输入部; 帧内插处理部，通过在构成实时视频的帧的图像之间插入内插图像，执行用于生成并输出预先设定的帧速率的内插视频的处理; 以及控制部分，当进行用于冻结显示在显示部分上的视频的指令时，操作以使得构成实时视频的帧的静止图像显示在显示部分上。

公开(公告)号：US5640351A

公开(公告)日：1997-06-17

申请号：US601859

申请日：1996-02-15

申请人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

发明人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/10

摘要： According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

摘要翻译： 根据本发明，通过选择列来形成多个存储单元阵列共用的数据总线，以防止发生数据冲突。 具体地说，两个存储单元阵列共有数据总线。 列解码器被提供有控制信号以控制列选择逻辑电路。 列选择逻辑电路被如此控制，以便在同时访问两个单元阵列期间防止响应于控制信号读出到数据总线的数据彼此相冲突。

公开(公告)号：US09065242B2

公开(公告)日：2015-06-23

申请号：US13474053

申请日：2012-05-17

申请人： Jeffrey R. Chen ,  Kenji Numata ,  Stewart T. Wu ,  Guangning Yang

发明人： Jeffrey R. Chen ,  Kenji Numata ,  Stewart T. Wu ,  Guangning Yang

IPC分类号： H01S3/10 ,  H01S5/0625 ,  G01S7/484 ,  H01S3/13 ,  H01S5/0687

CPC分类号： H01S5/06256 ,  G01S7/484 ,  H01S3/1304 ,  H01S3/1305 ,  H01S5/0687

摘要： An apparatus and method is provided to enable precision and fast laser frequency tuning. For instance, a fast tunable slave laser may be dynamically offset-locked to a reference laser line using an optical phase-locked loop. The slave laser is heterodyned against a reference laser line to generate a beatnote that is subsequently frequency divided. The phase difference between the divided beatnote and a reference signal may be detected to generate an error signal proportional to the phase difference. The error signal is converted into appropriate feedback signals to phase lock the divided beatnote to the reference signal. The slave laser frequency target may be rapidly changed based on a combination of a dynamically changing frequency of the reference signal, the frequency dividing factor, and an effective polarity of the error signal. Feed-forward signals may be generated to accelerate the slave laser frequency switching through laser tuning ports.

摘要翻译： 提供了一种能够实现精确和快速的激光频率调谐的装置和方法。 例如，使用光锁相环可以将快速可调的从属激光器动态地偏置锁定到参考激光线。 从属激光器与参考激光线进行外差，以产生随后频率分频的节拍。 可以检测分割的拍子和参考信号之间的相位差，以产生与相位差成比例的误差信号。 误差信号被转换成适当的反馈信号，以将分频的beatnote锁定到参考信号。 可以基于参考信号的动态变化的频率，分频因子和误差信号的有效极性的组合来快速地改变从属激光频率目标。 可以产生前馈信号，以通过激光调谐端口加速从属激光器频率切换。