公开(公告)号：US06924539B2

公开(公告)日：2005-08-02

申请号：US10233115

申请日：2002-08-30

Applicant: Manish Sharma ,  Lung Tran

Inventor： Manish Sharma ,  Lung Tran

IPC: H01L21/00 ,  H01L27/22 ,  H01L29/82 ,  H01L47/00

CPC classification number: H01L27/222 ,  H01L43/08

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract translation: 示例性非易失性存储器阵列包括衬底和形成在衬底上的多个存储器单元，每个存储器单元可在操作期间通过至少第一和第二导体寻址。 示例性存储器阵列中的示例性存储器单元包括具有开口的铁磁环形数据层，该开口使得第二导体能够电接触第一导体，环形数据层的至少一部分上的中间层和软参考 层在中间层的至少一部分上。

公开(公告)号：US20050063223A1

公开(公告)日：2005-03-24

申请号：US10668405

申请日：2003-09-22

Applicant: Lung Tran

Inventor： Lung Tran

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/14

CPC classification number: G11C11/15

Abstract: This invention provides a thermal-assisted switching magnetic memory storage device. In a particular embodiment, a cross-point array of conductive rows and columns is provided with offset tunnel junction magnetic memory cells provided proximate to the intersections between the rows and columns. A looping write conductor is provided close to, but not in electrical contact with each memory cell. The looping write conductor loops across the top and bottom of each memory cell. Each magnetic memory cell provides a magnetic data layer characterized by a material wherein the coercivity is decreased upon an increase in temperature, an intermediate layer, and a reference layer. The magnetic fields provided by the looping write conductor during a write operation are not sufficient to alter the magnetic orientation of an unheated data layer, but may alter the data layer of a memory cell warmed by a bias current tunneling through the memory cell.

Abstract translation: 本发明提供一种热辅助切换磁存储器存储装置。 在特定实施例中，导电行和列的交叉点阵列设置有靠近行和列之间的交叉点设置的偏移隧道结磁存储单元。 环形写导体靠近但不与每个存储单元电接触。 循环写入导体环绕每个存储单元的顶部和底部。 每个磁存储单元提供一个磁性数据层，其特征在于其中矫顽力在温度升高时降低，中间层和参考层。 在写入操作期间由循环写入导体提供的磁场不足以改变未加热的数据层的磁性取向，而是可以改变通过穿过存储器单元的偏置电流加热的存储器单元的数据层。

公开(公告)号：US20050052902A1

公开(公告)日：2005-03-10

申请号：US10657519

申请日：2003-09-08

Applicant: Kenneth Smith ,  Thomas Anthony ,  Lung Tran

Inventor： Kenneth Smith ,  Thomas Anthony ,  Lung Tran

IPC: G11C11/15 ,  G11C11/00

CPC classification number: G11C11/15 ,  G11C11/1675

Abstract: A memory device including an array of magnetic storage cells is disclosed. Each magnetic storage cell in the array includes a set of conductors used to write data to a storage cell and a second set of conductors used to heat the magnetic storage cell and read data from the magnetic storage cell. The magnetic storage cells can be used in electronic systems such as a computer system or consumer electronic system.

Abstract translation: 公开了一种包括磁存储单元阵列的存储器件。 阵列中的每个磁存储单元包括用于向存储单元写入数据的一组导体和用于加热磁存储单元并从磁存储单元读取数据的第二组导体。 磁存储单元可用于诸如计算机系统或消费电子系统的电子系统中。

公开(公告)号：US20050018475A1

公开(公告)日：2005-01-27

申请号：US10624175

申请日：2003-07-22

Applicant: Lung Tran ,  Thomas Anthony

Inventor： Lung Tran ,  Thomas Anthony

IPC: G11C11/15 ,  G11C11/16 ,  G11C11/00

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

公开(公告)号：US06649423B2

公开(公告)日：2003-11-18

申请号：US09971347

申请日：2001-10-04

Applicant: Thomas Anthony ,  Lung Tran ,  Manish Sharma

Inventor： Thomas Anthony ,  Lung Tran ,  Manish Sharma

IPC: H01L2100

CPC classification number: G11C11/16 ,  Y10S257/902

Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.

Abstract translation: 通过形成固定和感应层制造磁性隧道结; 并重新设定至少一层的磁化矢量。

公开(公告)号：US07391641B2

公开(公告)日：2008-06-24

申请号：US11285991

申请日：2005-11-23

Applicant: Manish Sharma ,  Lung Tran ,  Thomas C. Anthony

Inventor： Manish Sharma ,  Lung Tran ,  Thomas C. Anthony

IPC: G11C11/00

CPC classification number: G11C11/15 ,  H01L27/222 ,  H01L43/08

Abstract: An exemplary memory array including a plurality of memory cells, each of the memory cells comprises a first ferromagnetic layer, a second ferromagnetic layer spaced apart from the first ferromagnetic layer by a non-magnetic separating layer and being magnetically coupled to the first ferromagnetic layer by demagnetizing fields from the first ferromagnetic layer, a spacer layer above the second ferromagnetic layer, and a reference layer above the spacer layer. The first ferromagnetic layer, non-magnetic separating layer, and second ferromagnetic layer in combination function as a data layer of the memory cell.

Abstract translation: 包括多个存储器单元的示例性存储器阵列，每个存储器单元包括第一铁磁层，通过非磁性分离层与第一铁磁层隔开的第二铁磁层，并且通过非磁性分离层磁耦合到第一铁磁层，并通过 来自第一铁磁层的去磁场，第二铁磁层上方的间隔层，以及间隔层上方的基准层。 第一铁磁层，非磁性分离层和第二铁磁层组合起来作为存储单元的数据层。

公开(公告)号：US20060082526A1

公开(公告)日：2006-04-20

申请号：US10969085

申请日：2004-10-20

Applicant: Thomas Anthony ,  Lung Tran ,  Gary Gibson

Inventor： Thomas Anthony ,  Lung Tran ,  Gary Gibson

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/2011 ,  G09G3/3216 ,  G09G3/3283 ,  G09G2300/06 ,  G09G2300/0809 ,  G09G2300/0885 ,  G09G2310/0205 ,  G09G2310/0262

Abstract: A display element includes a variable optical element that changes appearance in response to changes in current, and a programmable resistance in series with the variable optical element. The resistance of the programmable resistance decreases in response to a first current in a first direction. The resistance of the programmable resistance increases in response to a second current in a second direction.

Abstract translation: 显示元件包括响应于电流变化而改变外观的可变光学元件和与可变光学元件串联的可编程电阻。 可编程电阻的电阻响应于第一方向上的第一电流而减小。 可编程电阻的电阻响应于第二方向上的第二电流而增加。

公开(公告)号：US06906941B2

公开(公告)日：2005-06-14

申请号：US10624175

申请日：2003-07-22

Applicant: Lung Tran ,  Thomas C. Anthony

Inventor： Lung Tran ,  Thomas C. Anthony

IPC: G11C11/15 ,  G11C11/16 ,  G11C5/08

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract translation: 本发明包括堆叠磁存储器结构。 磁存储器结构包括堆叠磁存储器结构。 第一层包括第一多个磁性隧道结。 形成与第一层相邻的第二层。 第二层包括第二多个磁性隧道结。 层叠的磁存储器结构还包括连接到第一多个磁隧道结中的每一个和第二多个磁性隧道结的公共第一组导体。

公开(公告)号：US06842389B2

公开(公告)日：2005-01-11

申请号：US10346700

申请日：2003-01-17

Applicant: Frederick A. Perner ,  James R. Eaton, Jr. ,  Kenneth K. Smith ,  Ken Eldredge ,  Lung Tran

Inventor： Frederick A. Perner ,  James R. Eaton, Jr. ,  Kenneth K. Smith ,  Ken Eldredge ,  Lung Tran

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C7/02 ,  G11C7/00

CPC classification number: G11C11/16

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract translation: 一种包括存储器单元阵列的四导体MRAM器件，每个存储器单元包括第一磁性层，电介质和第二磁性层; 多个局部列感测线，其中一个电连接到存储器单元阵列的第一磁性层; 多个局部行感测线，其中本地行读出线之一电连接到存储器单元阵列的第二磁性层; 平行于所述多个局部列感测线的多个全局列写入线; 平行于多个局部行感测线的多个全局行写行; 并且其中所述多个局部列感测线和所述多个本地行读传感线被连接以从所述存储器单元阵列读取数据，并且所述多个全局列写行和所述多个全局行写行被连接以将数据写入 存储单元阵列。

公开(公告)号：US06803274B2

公开(公告)日：2004-10-12

申请号：US10233109

申请日：2002-08-30

Applicant: Manish Sharma ,  Lung Tran

Inventor： Manish Sharma ,  Lung Tran

IPC: H01L21336

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract translation: 示例性非易失性存储器阵列包括衬底和形成在衬底上的多个存储器单元，每个存储器单元可在操作期间通过至少第一和第二导体寻址。 示例性存储器阵列中的示例性存储器单元包括具有开口的铁磁环形数据层，该开口使得第二导体能够电接触第一导体，环形数据层的至少一部分上的中间层和软参考 层在中间层的至少一部分上。