公开(公告)号：US20080233664A1

公开(公告)日：2008-09-25

申请号：US12073493

申请日：2008-03-06

Applicant: Michihiro Ebe ,  Masao Okihara

Inventor： Michihiro Ebe ,  Masao Okihara

IPC: H01L21/66 ,  C23F1/08

CPC classification number: H01L22/20 ,  H01L21/2007 ,  H01L22/12

Abstract: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data. The semiconductor integrated circuit production device also includes a surface treatment unit that adjusts SOI layer thickness by carrying out the surface treatment on the SOI layers in accordance with the decided conditions.

Abstract translation: 半导体集成电路制造方法制备将每个SOI层厚度的测量数据与每个SOI衬底识别数据相关联的SOI层厚度数据库。 该制造方法从SOI层厚度数据库中提取每个SOI衬底的测量数据，并且基于这些数据对SOI衬底进行层厚调整表面处理。 半导体集成电路制造装置包括用于存储SOI层厚度数据库的SOI层厚度数据库存储单元和用于从SOI层厚度数据库提取每个SOI衬底的测量数据的层厚调整条件控制单元， 基于这些数据的层厚调整表面处理。 半导体集成电路制造装置还包括：表面处理单元，其通过根据所确定的条件对SOI层进行表面处理来调整SOI层的厚度。

公开(公告)号：US20070080404A1

公开(公告)日：2007-04-12

申请号：US11533370

申请日：2006-09-20

Applicant: Taketo FUKURO ,  Masao OKIHARA

Inventor： Taketo FUKURO ,  Masao OKIHARA

IPC: H01L23/62

CPC classification number: H01L27/1203 ,  H01L27/0251 ,  H01L29/41733 ,  H01L29/665

Abstract: A semiconductor device includes a substrate, a first oxide film lying on the substrate, a thin semiconductor film lying on the first oxide film, a first terminal formed on the semiconductor film, a second terminal formed on the semiconductor film, a semiconductor element formed on the semiconductor film and electrically connected between the first and second terminals, and a protective diode formed on the semiconductor film and electrically connected in between the second and first terminal in a forward direction.

Abstract translation: 半导体器件包括基板，位于基板上的第一氧化物膜，位于第一氧化膜上的薄半导体膜，形成在半导体膜上的第一端子，形成在半导体膜上的第二端子，形成在半导体膜上的半导体元件 半导体膜，电连接在第一和第二端子之间，形成在半导体膜上的保护二极管，并在第二端子和第一端子之间沿正向电连接。

公开(公告)号：US20050176184A1

公开(公告)日：2005-08-11

申请号：US10963835

申请日：2004-10-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/092 ,  H01L29/45 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8234 ,  H01L29/74

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer. In addition, drain and source regions are formed by performing the ion implantation to the remaining second semiconductor layer with the gate electrode serving as a mask. Annealing to activate the substrate contact region, the drain region and the source region is then performed. Thereafter, a metal layer with a high melting point is formed on the drain and source regions and the metal layer is silicided through heat treatment.

Abstract translation: 本发明充分激活支撑衬底的衬底接触区域，而基本上不改变传统的SOI-CMOS器件形成过程。 支撑基板的露出面形成在分层基板的元件隔离区域中，该层叠基板的元件隔离区域包括具有第一半导体层的支撑基板，设置在支撑基板上的绝缘层，以及设置在绝缘层上的第二半导体层， 通过蚀刻掉绝缘层和第二半导体层。 然后通过从支撑衬底的暴露面的侧面进行离子注入，在支撑衬底中形成衬底接触区域。 此后，在支撑基板的露出面上形成元件隔离绝缘层，在剩余的第二半导体层上形成栅氧化膜和栅电极。 此外，通过以栅电极作为掩模对剩余的第二半导体层进行离子注入来形成漏极和源极区。 然后进行退火以激活基板接触区域，漏极区域和源极区域。 此后，在漏极和源极区域上形成具有高熔点的金属层，并且通过热处理将金属层硅化。

公开(公告)号：US06876039B2

公开(公告)日：2005-04-05

申请号：US10739200

申请日：2003-12-19

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/119

CPC classification number: H01L27/1203

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between N-channel and P-channel MOSFETs. A support substrate, an insulating layer on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in a first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in a second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region in the second channel part, although bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Abstract translation: 阈值电压对调整偏置电压的依赖性在N沟道和P沟道MOSFET之间变化。 支撑基板，支撑基板上的绝缘层和分别形成在绝缘层上的岛状的第一和第二硅层; 由完全耗尽的SOI形成的第一MOSFET，其中第一沟道部分形成在第一硅层中; 以及由部分耗尽的SOI形成的第二MOSFET，其中第二沟道部分形成在第二硅层中，第二MOSFET配置与第一MOSFET的互补MOSFET。 由于部分耗尽的SOI形成的第二MOSFET的阈值电压几乎不变化，因为第二通道部分中的中性区域，尽管偏压被施加到支撑衬底以改变由完全耗尽的第一MOSFET形成的第一MOSFET的阈值电压 所以我。