公开(公告)号：US20080142606A1

公开(公告)日：2008-06-19

申请号：US11612480

申请日：2006-12-19

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: G06K19/06

CPC classification number: G06K19/06028 ,  G06K19/06046 ,  G06K19/067

Abstract: An invention relating to an eFuse bar code structure and a method of using the bar code structure is disclosed. The bar code structure includes a substrate and a plurality of eFuse elements disposed on the substrate and arranged in a form of an array, such that a bar pattern can be formed by the result of whether the fuse of the eFuse elements is blown or not. The method of using the bar code structure includes, with respect to a data, fuses of the eFuse elements in the bar code structure being correspondingly blown in accordance with an encoding method to form a bar pattern. The eFuse bar code structure according to the present invention can be manufactured by using a semiconductor manufacturing process, and thus it has small volume, a high density and may record a huge number of data.

Abstract translation: 公开了与eFuse条形码结构相关的发明和使用该条形码结构的方法。 条形码结构包括基板和多个eFuse元件，其设置在基板上并且以阵列的形式布置，使得可以通过eFuse元件的熔丝是否熔断来形成条形图案。 使用条形码结构的方法包括相对于数据，条形码结构中的eFuse元件的熔丝根据编码方法相应地被吹制以形成条形图案。 根据本发明的eFuse条形码结构可以通过使用半导体制造工艺制造，因此其体积小，密度高，并且可以记录大量的数据。

公开(公告)号：US20080088783A1

公开(公告)日：2008-04-17

申请号：US11609334

申请日：2006-12-12

Applicant: Meng-Chieh Tai ,  Chih-Chung Liu ,  Yueh-Ping Chang

Inventor： Meng-Chieh Tai ,  Chih-Chung Liu ,  Yueh-Ping Chang

IPC: G02F1/1337

CPC classification number: G02F1/13624 ,  G02F1/133707 ,  G02F1/136213 ,  G02F1/1393 ,  G02F2001/134345

Abstract: A pixel structure suitable for being controlled by a scan line and a data line disposed on a thin film transistor (TFT) array substrate of a multi-domain vertical alignment (MVA) liquid crystal display is disclosed. The pixel structure includes a first TFT, a second TFT, a first pixel electrode, a second pixel electrode and a plurality of alignment members, wherein the first TFT and the second TFT are both electrically connected to the scan line and the data line. The first TFT has a first drain and the first pixel electrode is electrically connected to the first drain. The second TFT has a second drain and the second pixel electrode is floated over the second drain to form a coupling capacitor, while a voltage difference is established between the second pixel electrode and the first pixel electrode. The alignment members are disposed on the first and the second pixel electrode.

Abstract translation: 公开了适用于由多域垂直取向（MVA）液晶显示器的薄膜晶体管（TFT）阵列基板上的扫描线和数据线控制的像素结构。 像素结构包括第一TFT，第二TFT，第一像素电极，第二像素电极和多个对准部件，其中第一TFT和第二TFT都电连接到扫描线和数据线。 第一TFT具有第一漏极，并且第一像素电极电连接到第一漏极。 第二TFT具有第二漏极，并且第二像素电极浮在第二漏极上以形成耦合电容器，同时在第二像素电极和第一像素电极之间建立电压差。 对准构件设置在第一和第二像素电极上。

公开(公告)号：US20070235853A1

公开(公告)日：2007-10-11

申请号：US11399129

申请日：2006-04-05

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.

Abstract translation: 提供了包括基板，第一芯片和第二芯片的芯片封装结构。 衬底的第一触点和第二触点分别布置成位于衬底的第一侧区域和第二侧区域上。 所述第一芯片设置在所述基板上，并且具有布置成位于所述第一芯片的与所述第一触点相邻的第一引线接合区域上并且经由多个第一布线电连接到所述第一触点的多个第一焊盘。 第二芯片设置在远离第一芯片的对称中心的第一芯片上。 第二芯片具有多个第二接合焊盘，布置成位于与第二触点相邻的第二芯片的第二引线接合区域上，并且经由多个第二引线电连接到第二触点。

公开(公告)号：US07271048B2

公开(公告)日：2007-09-18

申请号：US11202733

申请日：2005-08-12

Applicant: Chien-Ping Chang ,  Mao Song Tseng ,  Hsin Huang Hsieh ,  Tien-Min Yuan

Inventor： Chien-Ping Chang ,  Mao Song Tseng ,  Hsin Huang Hsieh ,  Tien-Min Yuan

IPC: H01L21/336

CPC classification number: H01L29/7834 ,  H01L29/66553 ,  H01L29/66621

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract translation: 公开了一种制造具有高电池密度的沟槽MOSFET的方法。 该方法引入用于缩小沟槽结构的开口的侧壁氧化物间隔物，从而减小存储单元的单元间距。 此外，源结构通过额外的接触硅蚀刻自动形成，以防止在现有技术的离子注入期间光致抗蚀剂提升。 另一方面，接触结构填充有W型插头，用于克服根据现有技术用AlSiCu填充接触结构导致的不良金属台阶覆盖缺陷。 因此，可以增加器件的细胞密度; 并且可以减少设备的Rds-on和功率损耗。

公开(公告)号：US20070177558A1

公开(公告)日：2007-08-02

申请号：US11344059

申请日：2006-01-31

Applicant: Naga Ayachitula ,  Andrew Bradfield ,  Shu-Ping Chang ,  James Lipscomb

Inventor： Naga Ayachitula ,  Andrew Bradfield ,  Shu-Ping Chang ,  James Lipscomb

IPC: H04Q7/24

CPC classification number: H04W28/18 ,  H04W64/00

Abstract: A method, system and computer program and method for delivering a streaming data to a remote device from a wireless transmitter. In one embodiment, a transmitter is configured to send units of the streaming data to the remote device. A receiver is configured to receive usage data about the streaming data from the remote device. An adjusting module is configured to automatically adjust a transmission strategy of unsent units of the streaming data based, at least in part, on the usage data as a function of time according to a transmission policy. The usage data may include at least location information about the remote device or time of day information at the remote device. A user interface at the remote device may be configured to adjust the predefined transmission policy.

Abstract translation: 一种用于从无线发射机向远程设备传送流数据的方法，系统和计算机程序和方法。 在一个实施例中，发射机被配置为将流数据的单元发送到远程设备。 接收器被配置为从远程设备接收关于流数据的使用数据。 调整模块被配置为至少部分地基于根据传输策略的时间的函数的使用数据来自动调整流传输数据的未发送单元的传输策略。 使用数据可以至少包括关于远程设备的位置信息或在远程设备处的时间信息。 可以将远程设备处的用户界面配置为调整预定义的传输策略。

公开(公告)号：US20070102792A1

公开(公告)日：2007-05-10

申请号：US11308511

申请日：2006-03-31

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/544

CPC classification number: H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layer crack stop structure is described, disposed entirely in a die, entirely in a scribe line region outside the die, or partially in the die and partially in the scribe line region. The multi-layer crack stop structure is formed by stacking multiple layers of hollow crack stop units. The multi-layer crack stop structure can effectively prevent some damages like chipping, delamination or peeling-off from occurring to the active circuit region when the wafer is being sawn or when the die is subject to thermal cycles for testing, so that a better die can be obtained and the reliability of the packaged die can be significantly improved.

Abstract translation: 描述了多层裂纹停止结构，其完全设置在模具中，完全在模具外部的划线区域中，或者部分地设置在模具中，部分地设置在划线区域中。 多层裂缝停止结构通过堆叠多层中空裂缝停止单元形成。 多层裂纹停止结构可以有效地防止当晶片被锯切时或当模具经受热循环以进行测试时，有源电路区域发生切屑，分层或剥离等一些损坏，从而更好的模具 可以显着提高包装模具的可靠性。

公开(公告)号：US20070031287A1

公开(公告)日：2007-02-08

申请号：US11504303

申请日：2006-08-15

Applicant: James Webster ,  Ping Chang ,  Shaw-Tzuv Wang ,  Chi-Chen Chen ,  Rong-I Hong

Inventor： James Webster ,  Ping Chang ,  Shaw-Tzuv Wang ,  Chi-Chen Chen ,  Rong-I Hong

IPC: G01N33/00

CPC classification number: B01L3/502738 ,  B01L3/50273 ,  B01L2200/10 ,  B01L2300/0816 ,  B01L2300/0867 ,  B01L2300/0883 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0605 ,  B01L2400/0638 ,  F04B43/02 ,  F04B43/043 ,  Y10T436/2575

Abstract: The present invention provides a method for combining a fluid delivery system with an analysis system for performing immunological or other chemical of biological assays. The method comprises a miniature plastic fluidic cartridge containing a reaction chamber with a plurality of immobilized species, a capillary channel, and a pump structure along with an external linear actuator corresponding to the pump structure to provide force for the fluid delivery. The plastic fluidic cartridge can be configured in a variety of ways to affect the performance and complexity of the assay performed.

公开(公告)号：US20060186465A1

公开(公告)日：2006-08-24

申请号：US11329870

申请日：2006-01-10

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

IPC: H01L31/113

CPC classification number: H01L29/7811 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

公开(公告)号：US20050025064A1

公开(公告)日：2005-02-03

申请号：US10813865

申请日：2004-03-31

Applicant: Shu-Ping Chang ,  Fei Li ,  James Lipscomb

Inventor： Shu-Ping Chang ,  Fei Li ,  James Lipscomb

IPC: H04L12/24 ,  H04L12/26 ,  H04J3/14

CPC classification number: H04L41/5019 ,  H04L41/0853 ,  H04L41/5003

Abstract: Techniques for adaptive QoS include selecting, based on one or more QoS criteria corresponding to a client, one or more given data items suitable for sending to the client in response to a query from the client. The one or more given data items are selected from a set of data items. One or more statistics are associated with the one or more data items. The one or more statistics are useable to modify which data items are included in the set of data items. The statistics may be used by removing unpopular data items, as determined by the statistics, from the set of data items in the communication system. Additionally, data items exceeding the one or more QoS criteria can be transcoded to create new data items meeting the one or more QoS criteria, and the new data items can be added to the set of data items in the communication system. Thus, the set of data items can be changed depending on current demand by users for particular data items.

Abstract translation: 用于自适应QoS的技术包括基于与客户端相对应的一个或多个QoS准则来选择适合于响应于来自客户端的查询向客户端发送的一个或多个给定数据项。 从一组数据项中选择一个或多个给定的数据项。 一个或多个统计信息与一个或多个数据项相关联。 一个或多个统计数据可用于修改数据项集合中包含哪些数据项。 可以通过从通信系统中的数据项集合中去除由统计信息确定的不受欢迎的数据项来使用统计信息。 另外，超过一个或多个QoS准则的数据项目可以进行转码，以创建满足一个或多个QoS准则的新数据项，并且可以将新数据项添加到通信系统中的数据项集合。 因此，可以根据用户对特定数据项的当前需求来改变数据项集。

公开(公告)号：US20050009277A1

公开(公告)日：2005-01-13

申请号：US10771808

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

Inventor： Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7813

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region. Afterward, an isolation layer and a source metal contact layer are deposited over the structure, in which the isolation layer is utilized to protect the polysilicon gates, and also the source metal contact layer is utilized to ground both the body region and the polysilicon plate.

Abstract translation: 本发明的实施例提供了一种DMOS器件的端接结构及其形成方法。 在形成端接结构时，提供其上形成有外延层的硅衬底。 然后选择性地蚀刻通过掺杂外延层限定的体区，以在其中形成多个DMOS沟槽。 此后，在体区域的暴露表面上形成栅极氧化物层，并且形成终止氧化物层以环绕身体区域。 之后，在所有暴露的表面上沉积多晶硅层，然后选择性地蚀刻以在DMOS沟槽中形成多个多晶硅栅极，以及在端接氧化物层上具有朝向主体区域的延伸部分的多晶硅板。 通过使用端接多晶硅层作为注入掩模，在体区中形成源。 之后，在结构上沉积隔离层和源极金属接触层，其中隔离层用于保护多晶硅栅极，并且源极金属接触层用于接地体区域和多晶硅板。