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31.发明申请公开(公告)号：US20250068335A1
公开(公告)日：2025-02-27
申请号：US18944960
申请日：2024-11-12
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic RUELLE , Michel JAOUEN
IPC: G06F3/06
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
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公开(公告)号：US12160117B2
公开(公告)日：2024-12-03
申请号：US18154394
申请日：2023-01-13
Inventor： Lionel Cimaz , Antonio Borrello , Simone Ludwig Dalla Stella
Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.
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公开(公告)号：US12159043B2
公开(公告)日：2024-12-03
申请号：US17989389
申请日：2022-11-17
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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34.发明授权公开(公告)号：US12158941B2
公开(公告)日：2024-12-03
申请号：US17640680
申请日：2020-09-02
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic Ruelle
Abstract: The present disclosure relates to a method for authenticating instructions and operands in an electronic system comprising a controller. The method includes extracting instructions and operands via a first circuit of the controller from at least a first memory internal to the controller using a matrix bus of the controller, collecting, on the matrix bus, via a second circuit internal to the controller, instructions and operands during their transmission to the first circuit, and generating a word representative of the instructions and operands.
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公开(公告)号：US20240214010A1
公开(公告)日：2024-06-27
申请号：US18392372
申请日：2023-12-21
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Francois Sittler , Patrick Guyard
CPC classification number: H04B1/0096 , H04B1/0014 , H04B1/1607
Abstract: The present disclosure relates to a method for demodulating a RF signal comprising the steps of: detecting if an analog to digital converter (ADC) of a Near Zero Intermediate Frequency (NZIF) receiver is in a clipping state; and if yes: determining and storing a first value (RSSI1) representative of the energy of a received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a first intermediate frequency (IF1); determining and storing a second value (RSSI2) representative of the energy of the received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a second intermediate frequency (IF2) corresponding to the opposite value of the first intermediate frequency (IF1), selecting the intermediate frequency corresponding to the lowest value of said first and second values.
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Patent Agency Ranking
36.发明授权公开(公告)号：US11928339B2
公开(公告)日：2024-03-12
申请号：US17825975
申请日：2022-05-26
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic Ruelle , Michel Jaouen
IPC: G06F3/06
CPC classification number: G06F3/062 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L41/0803 , H04L49/109 , G06F21/85
CPC classification number: H04L49/109 , G06F21/85 , H04L41/0803
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US20240004804A1
公开(公告)日：2024-01-04
申请号：US18346512
申请日：2023-07-03
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Lionel Debieve
CPC classification number: G06F12/1458 , G06F21/64
Abstract: The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.
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39.发明授权公开(公告)号：US11775037B2
公开(公告)日：2023-10-03
申请号：US17540041
申请日：2021-12-01
Inventor： Loic Pallardy , Michael Soulie
IPC: G06F1/24 , G06F9/4401 , G06F13/40 , G06F11/14 , G06F15/78
CPC classification number: G06F1/24 , G06F9/4401 , G06F11/1441 , G06F13/4068 , G06F15/7807 , G06F2213/40
Abstract: The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
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公开(公告)号：US11700174B2
公开(公告)日：2023-07-11
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0803 , H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , G06F21/85
CPC classification number: H04L41/0813 , G06F15/177 , G06F15/17306 , H04L41/0803 , H04L49/109 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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